IP Library Granted Patent US 12,556,611
Granted Patent B2
US 12,556,611 · App. 18/603,988 · Granted Feb 17, 2026

Addressing and routing for devices using connectivity framework for embedded connectivity

Inventor: Paolo Trere (Santa Clara, CA)
Assignee: Microchip Technology Incorporated
H04L67/141H04L5/0044H04L45/745H04L63/061H04L63/0869H04L67/12H04L69/08H04L69/18H04L69/22
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Quick Facts
Patent No.
US 12,556,611
App. No.
18/603,988
Granted
Feb 17, 2026
Kind
B2
Abstract

An apparatus comprising a computing device including one or more processors, multiple peripheral communication devices, and a memory to store processor-executable instructions. The one or more processors are to perform operations of a gateway node comprising receiving a message from a first end node via a first one of the peripheral devices, the message including a source identifier comprising a first end node identifier assigned to the first end node and a destination identifier comprising a second end node identifier assigned to a second end node; consulting a routing table at least partially responsive to receiving the message; and forwarding the message to the second end node via a second one of the peripheral devices based on an entry in the routing table, the entry including an interface identifier stored in association with the second end node identifier, the interface identifier corresponding to the second one of the peripheral devices.

Claims (50)

1 . An apparatus comprising:

a computing device comprising one or more processors, multiple peripheral communication devices of different communication protocol types operably connected to the one or more processors, and a memory to store processor-executable instructions, the processor-executable instructions including an application and an application layer protocol stack to interface with the application, the application layer protocol stack to perform message communication processing between the application and respective input/output (I/O) buffers of the multiple peripheral communication devices, the processor-executable instructions such that, when executed by the one or more processors, cause the one or more processors to perform operations of a gateway node, the operations comprising:

receiving, in a message queue of the application, a message from a first end node via a first one of the multiple peripheral communication devices, the receiving of the message including the application layer protocol stack reading the message from a first I/O buffer of the first one of the multiple peripheral communication devices for storage in the message queue, the message including a source identifier comprising a first end node identifier assigned to the first end node and a destination identifier comprising a second end node identifier assigned to a second end node;

consulting a routing table at least partially responsive to receiving the message; and

storing the message in the message queue of the application for forwarding the message, at least partially based on an entry in the routing table, to the second end node via a second one of the multiple peripheral communication devices, the forwarding of the message including the application layer protocol stack writing the message from the message queue to a second I/O buffer of the second one of the multiple peripheral communication devices, the entry including an interface identifier stored in association with the second end node identifier, the interface identifier corresponding to the second one of the multiple peripheral communication devices.

2 . The apparatus of claim 1 , wherein the first end node identifier includes a cluster identifier and a first number appended to the cluster identifier, the second end node identifier includes the cluster identifier and a second number appended to the cluster identifier, and the cluster identifier matches a serial number of the gateway node.

3 . The apparatus of claim 2 , wherein the first end node identifier for routing messages via the gateway node is different from a serial number of the first end node, and the second end node identifier for routing messages via the gateway node is different from a serial number of the second end node.

4 . The apparatus of claim 2 , wherein the processor-executable instructions are to cause the one or more processors of the computing device to perform the operations comprising:

receiving a first enrollment message from the first end node;

at least partially responsive to receiving the first enrollment message:

assigning the first end node identifier to the first end node; and

sending a first response message to the first end node, the first response message including the first end node identifier;

receiving a second enrollment message from the second end node;

at least partially responsive to receiving the second enrollment message:

assigning the second end node identifier to the second end node; and

sending a second response message to the second end node, the second response message including the second end node identifier.

5 . The apparatus of claim 2 , wherein the processor-executable instructions are to cause the one or more processors of the computing device to perform the operations comprising:

distributing copies of the routing table to respective ones of the first end node and the second end node.

6 . The apparatus of claim 1 , wherein the processor-executable instructions are to cause the one or more processors of the computing device to perform the operations including receiving the message by:

reading, by the application layer protocol stack, one or more first data portions from the first I/O buffer of the first one of the multiple peripheral communication devices and storing, by the application layer protocol stack, the one or more first data portions in the message queue, until the message comprising the one or more first data portions is received via the first one of the multiple peripheral communication devices and stored in the message queue,

wherein the message has a message format according to a predetermined messaging protocol, the message includes a header and a payload, and the header includes the source identifier and the destination identifier.

7 . The apparatus of claim 6 , wherein the processor-executable instructions are to cause the one or more processors of the computing device to perform the operations including forwarding the message by:

writing, by the application layer protocol stack, one or more second data portions of the message from the message queue to the second I/O buffer of the second one of the multiple peripheral communication devices, until the message is transmitted via the second one of the multiple peripheral communication devices.

8 . The apparatus of claim 1 , wherein the message has a message format according to a unified messaging protocol which is common to messages received and forwarded through the multiple peripheral communication devices, the message including a header and a payload, the header including the source identifier and the destination identifier.

9 . The apparatus of claim 8 , wherein the message queue comprises a common message queue to store the messages received and forwarded through the multiple peripheral communication devices.

10 . The apparatus of claim 1 , wherein the multiple peripheral communication devices of the gateway node include three or more of a Universal Asynchronous Receiver-Transmitter (UART) device, an Inter-Integrated Circuit (I2C) device, a Serial Peripheral Interface (SPI) device, a Controller Area Network (CAN) device, a TIS device, a Bluetooth or Bluetooth Low Energy (BLE) device, and an IEEE 802.15.4 or low-rate wireless personal area network (LR-WPAN) device, and the multiple peripheral communication devices of the gateway node further include one or more of a Wi-Fi device, an Ethernet device, and a Universal Serial Bus (USB) device.

11 . A non-transitory processor-readable medium to store processor-executable instructions that, when executed by one or more processors of a computing device including multiple peripheral communication devices of different communication protocol types, cause the one or more processors to perform operations of a gateway node, the processor-executable instructions including an application and an application layer protocol stack to interface with the application, the application layer protocol stack to perform message communication processing between the application and respective input/output (I/O) buffers of the multiple peripheral communication devices, the operations comprising:

receiving, in a message queue of the application, a message from a first end node via a first one of the multiple peripheral communication devices, the receiving of the message including the application layer protocol stack reading the message from a first I/O buffer of the first one of the multiple peripheral communication devices for storage in the message queue, the message including a source identifier comprising a first end node identifier assigned to the first end node and a destination identifier comprising a second end node identifier assigned to a second end node;

consulting a routing table at least partially responsive to receiving the message; and

storing the message in the message queue of the application for forwarding the message, at least partially based on an entry in the routing table, to the second end node via a second one of the multiple peripheral communication devices, the forwarding of the message including the application layer protocol stack writing the message from the message queue to a second I/O buffer of the second one of the multiple peripheral communication devices, the entry including an interface identifier stored in association with the second end node identifier, the interface identifier corresponding to the second one of the multiple peripheral communication devices.

12 . The non-transitory processor-readable medium of claim 11 , wherein the first end node identifier includes a cluster identifier and a first number appended to the cluster identifier, the second end node identifier includes the cluster identifier and a second number appended to the cluster identifier, and the cluster identifier matches a serial number of the gateway node.

13 . The non-transitory processor-readable medium of claim 12 , wherein the processor-executable instructions are to cause the one or more processors of the computing device to perform the operations comprising:

receiving a first enrollment message from the first end node;

at least partially responsive to receiving the first enrollment message:

assigning the first end node identifier to the first end node; and

sending a first response message to the first end node, the first response message including the first end node identifier;

receiving a second enrollment message from the second end node;

at least partially responsive to receiving the second enrollment message:

assigning the second end node identifier to the second end node; and

sending a second response message to the second end node, the second response message including the second end node identifier.

14 . The non-transitory processor-readable medium of claim 12 , wherein the processor-executable instructions are to cause the one or more processors of the computing device to perform the operations comprising:

distributing copies of the routing table to respective ones of the first end node and the second end node.

15 . The non-transitory processor-readable medium of claim 12 , wherein the processor-executable instructions are to cause the one or more processors of the computing device to perform the operations including receiving the message by:

reading, by the application layer protocol stack, one or more first data portions from the first I/O buffer of the first one of the multiple peripheral communication devices and storing, by the application layer protocol stack, the one or more first data portions in the message queue, until the message comprising the one or more first data portions is received via the first one of the multiple peripheral communication devices and stored in the message queue,

wherein the message has a message format according to a predetermined messaging protocol, the message includes a header and a payload, and the header includes the source identifier and the destination identifier.

16 . The non-transitory processor-readable medium of claim 15 ,

wherein the processor-executable instructions are to cause the one or more processors of the computing device to perform the operations including forwarding the message by:

writing, by the application layer protocol stack, one or more second data portions of the message from the message queue to the second I/O buffer of the second one of the multiple peripheral communication devices, until the message is sent via the second one of the multiple peripheral communication devices.

17 . The non-transitory processor-readable medium of claim 11 , wherein the message has a message format according to a unified messaging protocol which is common to messages received and forwarded through the multiple peripheral communication devices of the gateway node, the message including a header and a payload, the header including the source identifier and the destination identifier.

18 . The non-transitory processor-readable medium of claim 11 , wherein the processor-executable instructions are to cause the one or more processors of the computing device to perform the operations with respect to the multiple peripheral communication devices including three or more of a Universal Asynchronous Receiver-Transmitter (UART) device, an Inter-Integrated Circuit (I2C) device, a Serial Peripheral Interface (SPI) device, a Controller Area Network (CAN) device, a TIS device, a Bluetooth or Bluetooth Low Energy (BLE) device, and an IEEE 802.15.4 or low-rate wireless personal area network (LR-WPAN) device, and with respect to the multiple peripheral communication devices further including one or more of a Wi-Fi device, an Ethernet device, and a Universal Serial Bus (USB) device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2025
From: TRERE, PAOLO
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 071838/0739 →
Continuity (2)
Provisional Application 63489828 · Mar 13, 2023
Related Publication 20240314209A1 · Sep 19, 2024
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