Buffer circuit for driving a GAN power switch and corresponding driver circuit
A buffer circuit for driving a GaN power switch includes an input node to receive an input signal and an output node to produce a gate signal for the GaN power switch. The buffer includes a push-pull stage that includes a first transistor coupled between a supply voltage node and the output node, a second transistor coupled between the supply voltage node and the output node, a third transistor coupled between the output node and a reference voltage node, and a fourth transistor coupled between the output node and the reference voltage node. The buffer includes a pre-buffer stage configured to receive the input signal and to produce respective driving signals for the first, second, third and fourth transistors to produce the gate signal at the output node in four consecutive phases.
1 . A driver circuit, comprising:
an input supply pad configured to receive a supply voltage, an input ground pad configured to receive a ground voltage, an input high-side control pad configured to receive a high-side control signal, an input low-side control pad configured to receive a low-side control signal, and an output pad configured to produce an output driving signal;
a high-side output buffer circuit;
a low-side output buffer circuit;
a level shifter configured to shift and pass the high-side control signal to the high-side output buffer circuit;
a low-side intermediate buffer circuit configured to pass the low-side control signal to the low-side output buffer circuit;
a high-side GaN power transistor arranged between a high-voltage supply pad and the output pad and driven by the high-side output buffer circuit;
a low-side GaN power transistor arranged between the output pad and a protected ground pad and driven by the low-side output buffer circuit;
a first voltage regulator configured to produce a first regulated voltage as a function of the supply voltage;
bootstrap circuitry configured to produce a bootstrap voltage as a function of the supply voltage; and
a second voltage regulator configured to produce a second regulated voltage as a function of the bootstrap voltage, wherein the low-side output buffer circuit is supplied by the first regulated voltage and the high-side output buffer circuit is supplied by the second regulated voltage.
2 . The driver circuit of claim 1 , wherein the level shifter, the high-side output buffer circuit, the low-side intermediate buffer circuit, the low-side output buffer circuit, the high-side GaN power transistor and the low-side GaN power transistor are implemented in a single GaN semiconductor substrate.
3 . The driver circuit of claim 2 , wherein the GaN semiconductor substrate is a GaN-on-Si semiconductor substrate.
4 . The driver circuit of claim 1 , wherein:
the level shifter, the low-side intermediate buffer circuit, the low-side output buffer circuit and the low-side GaN power transistor are implemented in a first GaN semiconductor substrate; and
the high-side output buffer circuit and the high-side GaN power transistor are implemented in a second GaN semiconductor substrate.
5 . The driver circuit of claim 4 , wherein the first and second GaN semiconductor substrates are GaN semiconductor substrates.
6 . A driver circuit, comprising:
an input supply pad configured to receive a supply voltage, an input ground pad configured to receive a ground voltage, an input high-side control pad configured to receive a high-side control signal, an input low-side control pad configured to receive a low-side control signal, and an output pad configured to produce an output driving signal;
a high-side output buffer circuit;
a low-side output buffer circuit;
a level shifter configured to shift and pass the high-side control signal to the high-side output buffer circuit;
a low-side intermediate buffer circuit configured to pass the low-side control signal to the low-side output buffer circuit;
a high-side GaN power transistor arranged between a high-voltage supply pad and the output pad and driven by the high-side output buffer circuit;
a low-side GaN power transistor arranged between the output pad and a protected ground pad and driven by the low-side output buffer circuit, wherein the low-side intermediate buffer circuit includes an input stage, a differential-to-single-ended stage, and an output stage, wherein the input stage includes:
an input differential pair of transistors, a first transistor of the pair being configured to receive an input signal at a control terminal thereof, and a second transistor of the pair being configured to receive a reference signal at a control terminal thereof;
a first current generator load coupled between the first transistor and a supply node of the low-side intermediate buffer circuit;
a second current generator load coupled between the second transistor and the supply node of the low-side intermediate buffer circuit; and
a tail current generator coupled between a tail node of the input differential pair of transistors and a ground node of the low-side intermediate buffer circuit;
and wherein the differential-to-single-ended stage includes a current mirror arrangement coupled to first and second output nodes of the input differential pair of transistors;
and wherein the output stage includes a pair of cascaded inverter circuits, the first inverter circuit being configured to receive a single-ended signal from an output node of the differential-to-single-ended stage, and the second inverter circuit being configured to receive a complemented signal from an output node of the first inverter circuit to produce an output signal of the low-side intermediate buffer circuit.
7 . The driver circuit of claim 6 , wherein the level shifter, the high-side output buffer circuit, the low-side intermediate buffer circuit, the low-side output buffer circuit, the high-side GaN power transistor and the low-side GaN power transistor are implemented in a single GaN semiconductor substrate.
8 . The driver circuit of claim 7 , wherein the GaN semiconductor substrate is a GaN-on-Si semiconductor substrate.
9 . The driver circuit of claim 6 , wherein:
the level shifter, the low-side intermediate buffer circuit, the low-side output buffer circuit and the low-side GaN power transistor are implemented in a first GaN semiconductor substrate; and
the high-side output buffer circuit and the high-side GaN power transistor are implemented in a second GaN semiconductor substrate.
10 . The driver circuit of claim 9 , wherein the first and second GaN semiconductor substrates are GaN semiconductor substrates.
11 . The driver circuit of claim 6 , further comprising:
a first voltage regulator configured to produce a first regulated voltage as a function of the supply voltage;
bootstrap circuitry configured to produce a bootstrap voltage as a function of the supply voltage; and
a second voltage regulator configured to produce a second regulated voltage as a function of the bootstrap voltage, wherein the low-side output buffer circuit is supplied by the first regulated voltage and the high-side output buffer circuit is supplied by the second regulated voltage.