REDUCED POWER CONSUMPTION CIRCUIT AND CORRESPONDING METHOD
A system on chip, SOC circuit comprising a plurality of peripherals configured to be clocked with respective clock signals, wherein the circuit comprises a clock controller configured to produce said respective clock signals via respective clock divide factors, the clock controller comprising a plurality of storage locations having stored therein respective sets of clock divide factors, wherein the clock controller comprises clock divide factor selection circuitry configured to select an operating set of clock divide factors out of said respective sets of clock divide factors stored in said plurality of storage locations and wherein the clock controller is configured to apply to the plurality of peripherals respective clock signals produced via the clock divide factors in the operating set of clock divide factors selected out of said respective sets of clock divide factors stored in said plurality of storage locations.
1 . A circuit comprising a plurality of peripherals configured to be clocked with respective clock signals, wherein the circuit comprises a clock controller configured to produce the respective clock signals via respective clock divide factors, the clock controller having stored therein respective sets of clock divide factors, wherein the clock controller comprises clock divide factor selection circuitry configured to select an operating set of clock divide factors out of the respective sets of clock divide factors and wherein the clock controller is configured to apply to the plurality of peripherals respective clock signals produced via the clock divide factors in the operating set of clock divide factors selected out of the respective sets of clock divide factors.
2 . The circuit of claim 1 , wherein the clock controller comprises a plurality of storage locations comprising a first storage location and a second storage location having stored therein a first set of clock divide factors and a second set of clock divide factors, respectively, wherein, in response to being clocked by respective clock signals produced via the second set of clock divide factors, the plurality of peripherals have a lower power absorption than when clocked by respective clock signals produced via the first set of clock divide factors.
3 . The circuit of claim 2 , wherein the clock divide factor selection circuitry in the clock controller is configured to receive a power status signal and to select the operating set of clock divide factors out of the first set and the second set of clock divide factors based on the power status signal.
4 . The circuit of claim 3 , comprising:
a consumption detector configured to monitor an amount of current absorbed by the circuit,
a power control logic unit configured to receive a current evaluation signal from the consumption detector and produce the power status signal based the current evaluation signal.
5 . The circuit of claim 4 , wherein the consumption detector is configured to have stored therein upper and lower threshold values for the current absorbed by the circuit, wherein the power control logic unit is configured to produce the power status signal based on a result of comparing the amount of current absorbed by the circuit with the upper and lower threshold values.
6 . The circuit of claim 5 , wherein the upper and lower threshold values are selectively adjustable.
7 . The circuit of claim 5 , wherein the consumption detector comprises counter circuitry configured to have count first and second counter values that are updated in response to the current absorbed by the circuit reaching the upper and lower threshold values respectively.
8 . The circuit of claim 6 , wherein the consumption detector comprises counter circuitry configured to have count first and second counter values that are updated in response to the current absorbed by the circuit reaching the upper and lower threshold values respectively.
9 . The circuit of claim 1 , wherein the circuit is configured to operate in a sequence of power cycles, and at least one set of clock divide factors in the sets of clock divide factors:
is stored in a non-volatile memory and loaded during a power cycle in the sequence of power cycles, or
is re-calculated during a power cycle in the sequence of power cycles.
10 . The circuit of claim 2 , wherein the circuit is configured to operate in a sequence of power cycles, and at least one set of clock divide factors in the sets of clock divide factors:
is stored in a non-volatile memory and loaded during a power cycle in the sequence of power cycles, or
is re-calculated during a power cycle in the sequence of power cycles.
11 . The circuit of claim 3 , wherein the circuit is configured to operate in a sequence of power cycles, and at least one set of clock divide factors in the sets of clock divide factors:
is stored in a non-volatile memory and loaded during a power cycle in the sequence of power cycles, or
is re-calculated during a power cycle in the sequence of power cycles.
12 . The circuit of claim 4 , wherein the circuit is configured to operate in a sequence of power cycles, and at least one set of clock divide factors in the sets of clock divide factors:
is stored in a non-volatile memory and loaded during a power cycle in the sequence of power cycles, or
is re-calculated during a power cycle in the sequence of power cycles.
13 . The circuit of claim 5 , wherein the circuit is configured to operate in a sequence of power cycles, and at least one set of clock divide factors in the sets of clock divide factors:
is stored in a non-volatile memory and loaded during a power cycle in the sequence of power cycles, or
is re-calculated during a power cycle in the sequence of power cycles.
14 . The circuit of claim 6 , wherein the circuit is configured to operate in a sequence of power cycles, and at least one set of clock divide factors in the sets of clock divide factors:
is stored in a non-volatile memory and loaded during a power cycle in the sequence of power cycles, or
is re-calculated during a power cycle in the sequence of power cycles.
15 . The circuit of claim 7 , wherein the circuit is configured to operate in a sequence of power cycles, and at least one set of clock divide factors in the sets of clock divide factors:
is stored in a non-volatile memory and loaded during a power cycle in the sequence of power cycles, or
is re-calculated during a power cycle in the sequence of power cycles.
16 . The circuit of claim 8 , wherein the circuit is configured to operate in a sequence of power cycles, and at least one set of clock divide factors in the sets of clock divide factors:
is stored in a non-volatile memory and loaded during a power cycle in the sequence of power cycles, or
is re-calculated during a power cycle in the sequence of power cycles.
17 . A method of configuring the circuit of claim 1 , wherein the method comprises the clock controller selecting a set of learning clock divide factors as a candidate operating set of clock divide factors, and
a) executing one or more tasks through the circuit with the plurality of peripherals clocked with respective clock signals produced via the set of learning clock divide factors,
b) checking circuit consumption and performance indicators in executing the one or more tasks against target consumption and performance specifications,
and
in response to the circuit consumption and performance indicators in executing the one or more tasks meeting the target consumption and performance specifications, selecting the learning clock divide factors as a configurated operating set of clock divide factors; or
in response to the circuit consumption and performance indicators in executing the one or more tasks failing to meet the target consumption and performance specifications repeating steps a) and b) with modified values for the set of learning clock divide factors.
18 . The method of claim 17 , wherein the circuit consumption and performance indicators in executing the one or more tasks comprise an execution cost defined via one of simulated annealing and tabu search.