IP Library Granted Patent US 12,619,519
Granted Patent B2
US 12,619,519 · App. 18/607,260 · Granted May 5, 2026

Apparatus and method for simulated virtual component development

Inventors: David Morse (Alexandria, VA); David Walsh (Alexandria, VA)
Assignee: Parry Labs, LLC
G06F11/3652G06F11/3698
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Quick Facts
Patent No.
US 12,619,519
App. No.
18/607,260
Granted
May 5, 2026
Kind
B2
Abstract

An apparatus for, and method of, simulated virtual component testing, including a processor and a memory, the processor configured to receive a specification datum, receive an application datum, generate emulation parameters as a function of the specification datum, generate a testing framework as a function of the emulation parameters, determine an integration datum as a function of the testing framework and the application datum, output a compatibility datum as a function of the integration datum, and display a user interface.

Claims (38)

1 . An apparatus for simulated virtual component development, the apparatus comprising:

at least a processor; and

at least a memory communicatively connected to the at least a processor, wherein the at least a memory contains instructions configuring the at least a processor to:

receive a specification datum;

receive an application datum;

generate emulation parameters as a function of the specification datum, wherein the emulation parameters comprise identification of an engineering methodology which includes a set of procedures to solve engineering problems, wherein the engineering methodology comprises an agile engineering technology;

execute the agile engineering methodology by iteratively testing sub-components of a component included in the specification datum followed by testing of a whole component;

generate a testing framework as a function of the emulation parameters and execution of the agile engineering methodology;

determine an integration datum by inputting into an integration machine learning model the testing framework and the application datum and receiving as an output from the integration machine learning model the integration datum, wherein the integration datum is generated within a containerized environment including a container image, wherein the container image includes a portable executable image combined with a manifest file;

output a compatibility datum as a function of the integration datum;

generate an automated artifact as a function of compatibility datum, wherein the automated artifact comprises data objects including at least executable files;

generate a deployment environment as a function of the automated artifact for further testing of the component, including its sub-components, wherein generating the deployment environment comprises:

implementing context insertion through a vector database, wherein the vector database is used to provide additional information for generating deployment environment; and

deploying the containerized environment; and

a display device configured to display a user interface for the compatibility datum.

2 . The apparatus of claim 1 , wherein at least one of the emulation parameters is configured to generate a digital twin.

3 . The apparatus of claim 2 , wherein the digital twin is configured to simulate at least a specification datum.

4 . The apparatus of claim 1 , wherein the specification datum comprises a specification of a Field Programmable Gate Array.

5 . The apparatus of claim 1 , wherein the specification datum comprises a specification of a Boot Operating Storage Solution Card.

6 . The apparatus of claim 1 , wherein the user interface is configured to display at least a layer of structural detail of the specification datum.

7 . A method of simulated virtual component development, the method comprising:

receiving, by at least a processor, a specification datum;

receiving, by the at least a processor, an application datum;

generating, by the at least a processor, emulation parameters as a function of the specification datum, wherein the emulation parameters comprise identification of an engineering methodology which includes a set of procedures to solve engineering problems, wherein the engineering methodology comprises an agile engineering technology;

executing, by the at least a processor, the agile methodology by iteratively testing sub-components of a component included in the specification datum followed by testing of a whole component;

generating, by the at least a processor, a testing framework as a function of the emulation parameters and execution of the agile engineering technology;

determining, by the at least a processor, an integration datum by inputting into an integration machine learning model the testing framework and the application datum and receiving as an output from the integration machine learning model the integration datum, wherein the integration datum is generated within a containerized environment including a container image, wherein the container image includes a portable executable image combined with a manifest file;

outputting, by the at least a processor, a compatibility datum as a function of the integration datum;

generating, by the at least a processor, an automated artifact as a function of compatibility datum, wherein the automated artifact comprises data objects including at least executable files;

generating, by the at least a processor, a deployment environment as a function of the automated artifact for further testing of the component, including its sub-components, wherein generating the deployment environment comprises:

implementing context insertion through a vector database, wherein the vector database is used to provide additional information for generating deployment environment; and

deploying the containerized environment; and

displaying, by a display device, a user interface for the compatibility datum.

8 . The method of claim 7 , wherein the at least one of the emulation parameters is configured to generate a digital twin.

9 . The method of claim 8 , wherein the digital twin is configured to simulate at least a specification datum.

10 . The method of claim 7 , wherein the specification datum comprises a specification of a Field Programmable Gate Array.

11 . The method of claim 7 , wherein the specification datum comprises a specification of a Boot Operating Storage Solution Card.

12 . The method of claim 7 , wherein the user interface is configured to display at least a layer of structural detail of the specification datum.

Assignments (2)
SECURITY INTEREST Recorded Dec 23, 2024
From: PARRY LABS, LLC; PARRY LABS HOLDINGS, LLC
To: TRIPLEPOINT CAPITAL LLC
Reel/Frame 069665/0281 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2024
From: MORSE, DAVID; WALSH, DAVID
To: PARRY LABS, LLC
Reel/Frame 067879/0182 →
Continuity (1)
Related Publication 20250291703A1 · Sep 18, 2025
References Cited (21)
US 9959199B2 · Ignatyev · 2018 [cited by applicant]
US 10963243B2 · Alexander · 2021 [cited by applicant]
US 11321054B2 · Gaitonde · 2022 [cited by applicant]
US 12072792B2 · Drozhak · 2024 [cited by examiner]
US 20130185594A1 · Budnik · 2013 [cited by examiner]
US 20130318397A1 · Jamison · 2013 [cited by examiner]
US 20160034382A1 · Kumar · 2016 [cited by examiner]
US 20160188445A1 · Hermeto · 2016 [cited by examiner]
US 20180239692A1 · Kalyanasundram · 2018 [cited by examiner]
US 20180324204A1 · McClory · 2018 [cited by examiner]
US 20190155970A1 · Matthews · 2019 [cited by examiner]
US 20190235994A1 · Epperlein · 2019 [cited by examiner]
US 20210081304A1 · Masis · 2021 [cited by examiner]
US 20210133210A1 · Kanagovi · 2021 [cited by examiner]
US 20220261240A1 · Abbas · 2022 [cited by examiner]
US 20220350641A1 · Gilmore · 2022 [cited by examiner]
US 20230028146A1 · Harwood · 2023 [cited by examiner]
US 20230125342A1 · Krishna · 2023 [cited by examiner]
US 20240095155A1 · Zhao · 2024 [cited by examiner]
US 20240160557A1 · Bolshakov · 2024 [cited by examiner]
CN 112130930B · 2023 [cited by applicant]