Conduction mode (CRM) control in digital power supply using mosfet drain-to-source edge detection
A method of operating a DC-DC converter includes generating a high-side control signal for a high-side transistor and generating a low-side control signal for a low-side transistor to thereby cause conversion of an input voltage to an output voltage. A time shift is measured between a falling edge of the low-side control signal and a time at which a drain-to-source voltage of the low-side transistor becomes higher than a set threshold voltage. A time shift error is determined as a difference between a dead time and the measured time shift, with the dead time being a time between the falling edge of the low-side control signal and a rising edge of the high-side control signal. A frequency of the high-side control signal and the low-side control signal is adjusted, based upon the time shift error, to maintain the DC-DC converter as operating in critical conduction mode.
1 . A method of operating a DC-DC converter, comprising:
generating a high-side control signal for a high-side transistor of the DC-DC converter and generating a low-side control signal for a low-side transistor of the DC-DC converter to thereby cause conversion of an input voltage to an output voltage;
measuring a time shift between a falling edge of the low-side control signal and a time at which a drain-to-source voltage of the low-side transistor becomes higher than a set threshold voltage;
determining a time shift error as a difference between a dead time and the measured time shift, with the dead time being a time between the falling edge of the low-side control signal and a rising edge of the high-side control signal; and
adjusting a frequency of the high-side control signal and the low-side control signal, based upon the time shift error, to maintain the DC-DC converter as operating in critical conduction mode.
2 . The method of claim 1 , wherein adjusting the frequency of the high-side control signal and the low-side control signal, based upon the time shift error, is performed by:
decreasing the frequency of the high-side control signal and the low-side control signal when the measured time shift is greater than the dead time.
3 . The method of claim 2 , further comprising maintaining the DC-DC converter as operating in the critical conduction mode, or switching operation of the DC-DC converter to the critical conduction mode, based upon the measured time shift being greater than the dead time.
4 . The method of claim 2 , wherein adjusting the frequency of the high-side control signal and the low-side control signal, based upon the time shift error, is performed by:
increasing the frequency of the high-side control signal and the low-side control signal when the measured time shift is less than the dead time.
5 . The method of claim 4 , further comprising maintaining the DC-DC converter as operating in the critical conduction mode based upon the measured time shift being less than the dead time.
6 . The method of claim 1 , further comprising changing the set threshold voltage to thereby change a level of negativity of the inductor current occurring during the dead time.
7 . The method of claim 1 , further comprising increasing the set threshold voltage to increase a level of negativity of the inductor current occurring during the dead time.
8 . The method of claim 1 , further comprising decreasing the set threshold voltage to decrease a level of negativity of the inductor current occurring during the dead time.
9 . A power converter, comprising:
a DC-DC converter including a high-side transistor and a low-side transistor, the DC-DC converter being operable to convert an input voltage to an output voltage;
pulse width modulation (PWM) circuitry configured to generate a high-side control signal for the high-side transistor and generate a low-side control signal for the low-side transistor to thereby cause conversion of the input voltage to the output voltage;
a comparator configured to assert its output in response to a drain-to-source voltage of the low-side transistor being greater than a set threshold voltage;
time-shift capture circuitry configured to measure a time shift between a falling edge of the low-side control signal and a time at which the comparator is asserted;
time-shift control circuitry configured to determine a time shift error as a difference between a dead time and the measured time shift, with the dead time being a time between the falling edge of the low-side control signal and a rising edge of the high-side control signal;
frequency adjustment circuitry configured to generate an output signal indicative of a frequency of the high-side control signal and the low-side control signal, based upon the time shift error, that would maintain the DC-DC converter as operating in critical conduction mode; and
a policy circuit configured to generate a PWM control signal for the PWM circuitry, based upon the output signal from the frequency adjustment circuitry;
wherein the PWM circuitry operates based upon the PWM control signal.
10 . The power converter of claim 9 , further comprising a coupling clamp configured to clamp the drain-to-source voltage of the low-side transistor and provide that clamped drain-to-source voltage to the comparator.
11 . The power converter of claim 10 , further comprising a digital-to-analog converter configured to generate the set threshold voltage.
12 . The power converter of claim 9 , wherein the frequency adjustment circuitry adjusts the frequency of the high-side control signal and the low-side control signal, based upon the time shift error, by decreasing the frequency of the high-side control signal and the low-side control signal when the measured time shift is greater than the dead time.
13 . The power converter of claim 12 , wherein the policy circuitry is further configured to maintain the DC-DC converter as operating in the critical conduction mode, or switch operation of the DC-DC converter to the critical conduction mode, based upon the measured time shift being greater than the dead time.
14 . The power converter of claim 12 , wherein the frequency adjustment circuitry adjusts the frequency of the high-side control signal and the low-side control signal, based upon the time shift error, by increasing the frequency of the high-side control signal and the low-side control signal when the measured time shift is less than the dead time.
15 . The power converter of claim 14 , wherein the policy circuitry is further configured to maintain the DC-DC converter as operating in the critical conduction mode based upon the measured time shift being less than the dead time.