Granted Patent B2

US 12,363,464 · App. 18/608,302 · Granted Jul 15, 2025

Inventors: Patrick Gallagher (Santa Clara, CA); Thomas W. Baehr-Jones (Santa Clara, CA); Michael Gao (Santa Clara, CA); Mitchell A. Nahmias (Santa Clara, CA)

Assignee: Luminous Computing, Inc.

H04Q11/0005H04B10/25

Abstract

Claims (97)

1. An optical link system, comprising:

a photonics substrate;

a plurality of optical links, each optical link of the plurality of optical links comprising:

one of a plurality of optical waveguides defined on the photonics substrate; and

one of a plurality of first optoelectronic transducers optically coupled to the optical waveguide; and/or one of a plurality of second optoelectronic transducers optically coupled to the optical waveguide; and

a plurality of electronics modules, comprising:

a plurality of first processor electronic modules, each first processor electronic module comprising:

a respective first electronics chip or chiplet mounted on the photonics substrate; and

a respective first processor core defined on the respective first electronics chip or chiplet;

a first switch configured for routing flows of data between each one of the plurality of first processor electronic modules and others of the plurality of electronics modules;

wherein the plurality of optical links communicatively couple the plurality of first processor electronic modules to the first switch;

wherein the plurality of electronics modules further comprises:

a plurality of first memory controller electronic modules configured for controlling the flows of data to and from system memory;

wherein the first switch is configured for routing the flows of data between each one of the plurality of first processor electronic modules and each one of the plurality of first memory controller electronic modules;

wherein the plurality of optical links communicatively couple the plurality of first memory controller electronic modules to the first switch;

wherein the plurality of electronics modules further comprises:

a plurality of second memory controller electronic modules configured for controlling the flows of data to and from the system memory; and

a second switch configured for routing the flows of data between each one of the plurality of first processor electronic modules and each one of the plurality of second memory controller electronics modules;

wherein the plurality of optical links communicatively couple the plurality of second memory modules to the second switch.

2. The system according to claim 1 , wherein each optical link further comprises:

a first grating coupler configured to couple light between one of the first optoelectronic transducers and a respective one of the plurality of optical waveguides; and

a second grating coupler configured to couple light between one of the second optoelectronic transducers and the respective one of the plurality of optical waveguides.

3. The system of claim 1 , wherein, for each of the plurality of first processor electronic modules, the respective first processor core comprises a matrix multiplication core.

4. The optical link system of claim 1 , wherein the plurality of optical links communicatively coupling each of the plurality of first processor electronic modules directly to the first switch include waveguide crossings.

5. The optical link system of claim 1 , wherein each of the plurality of optical links comprises a photonic interposer between each of the plurality of electronics modules and the photonics substrate configured for transducing signals between optical and electrical domains to enable communicative coupling of the plurality of electronics modules and the photonics substrate, wherein each photonic interposer includes one of the first optoelectronic transducers and one of the second optoelectronic transducers.

6. An optical link system, comprising:

a photonics substrate;

a plurality of optical links, each optical link of the plurality of optical links comprising:

one of a plurality of optical waveguides defined on the photonics substrate; and

one of a plurality of first optoelectronic transducers optically coupled to the optical waveguide, and/or one of a plurality of second optoelectronic transducers optically coupled to the optical waveguide; and

a plurality of electronics modules, comprising:

a plurality of first processor electronic modules, each first processor electronic module comprising:

a respective first electronics chip or chiplet mounted on the photonics substrate; and

a respective first processor core defined on the respective first electronics chip or chiplet;

a first switch configured for routing flows of data between each one of the plurality of first processor electronic modules and others of the plurality of electronics modules;

wherein the plurality of optical links communicatively couple the plurality of first processor electronic modules to the first switch;

wherein the plurality of electronics modules further comprises:

a plurality of second processor electronic modules, each second processor electronic module comprising:

a respective second electronics chip or chiplet mounted on the photonics substrate; and

a respective second processor core defined on the respective second electronics chip or chiplet; and

a second switch configured for routing the flows of data between each one of the plurality of second processor electronic modules and the first switch;

wherein the plurality of optical links communicatively couple the plurality of second processor electronic modules to the second switch.

7. The system according to claim 6 , wherein the plurality of electronics modules further comprises;

a plurality of first memory controller electronic modules configured for controlling flows of data to and from system memory;

wherein the first switch is configured for routing the flows of data between each one of the plurality of first processor electronic modules and each one of the plurality of first memory controller electronic modules; and

wherein the plurality of optical links communicatively couple the plurality of first memory controller electronic modules to the first switch.

8. The system according to claim 7 , wherein the first switch comprises an optical switch.

9. The system according to claim 7 , wherein the plurality of electronics modules further comprises:

a plurality of second memory controller electronic modules configured for controlling the flows of data to and from the system memory; and

wherein the plurality of optical links communicatively couple the plurality of second memory modules to the second switch.

10. The system according to claim 7 , wherein the second switch comprises an optical switch.

11. The system according to claim 6 , wherein the first switch and the second switch each comprise an optical switch.

12. The system according to claim 6 , wherein the plurality of electronics modules further comprises:

a plurality of third processor electronic modules, each third processor electronic module comprising:

a respective third electronics chip or chiplet mounted on the photonics substrate; and

a respective third processor core defined on the respective second electronics chip or chiplet;

a third switch configured for routing the flows of data between each one of the plurality of third processor electronic modules, the first switch and the second switch;

wherein the plurality of optical links communicatively couple the plurality of third processor electronic modules to the third switch.

13. An optical link system, comprising:

a photonics substrate;

a plurality of optical links, each optical link of the plurality of optical links comprising:

one of a plurality of optical waveguides defined on the photonics substrate; and

one of a plurality of first optoelectronic transducers optically coupled to the optical waveguide; and/or one of a plurality of second optoelectronic transducers optically coupled to the optical waveguide; and

a plurality of electronics modules, comprising:

a plurality of first processor electronic modules, each first processor electronic module comprising:

a respective first electronics chip or chiplet mounted on the photonics substrate; and

a respective first processor core defined on the respective first electronics chip or chiplet;

a first switch configured for routing flows of data between each one of the plurality of first processor electronic modules and others of the plurality of electronics modules;

wherein the plurality of optical links communicatively couple the plurality of first processor electronic modules to the first switch;

wherein: the plurality of first processor electronic modules defines a rectangular array comprising a plurality of rows and a plurality of columns;

each row of the plurality of rows comprises a first respective subset of at least three first processor electronic modules of the plurality of first processor electronic modules, wherein, for each row, each first processor electronic module of the row is communicatively connected directly to every other first processor electronic module of the row via a respective optical link of the plurality of optical links; and

each column of the plurality of columns comprises a second respective subset of at least three first processor electronic modules of the plurality of first processor electronic modules, wherein, for each column, each first processor electronic module of the column is communicatively connected directly to every other first processor electronic module of the column via a respective optical link of the plurality of optical links.

14. The system according to claim 13 , wherein the plurality of electronics modules further comprises:

a second switch configured for routing the flows of data between each one of the plurality of first processor electronic modules and other electronics modules;

wherein the plurality of optical links communicatively couple the plurality of first processor electronic modules to the second switch.

15. The system of claim 13 , wherein:

a first row of the plurality of rows comprises a first one of the first processor electronic modules and a second one of the first processor electronic module communicatively connected to the first one of the first processor electronic module via a first optical link;

a first column of the plurality of columns comprises the first one of the first processor electronic modules and a third one of the first processor electronic modules communicatively connected to the first one of the first processor electronic modules via a second optical link; and

the system is configured to:

at the second one of the first processor electronic modules: perform a first computation, generate a signal based on the computation, and transmit the signal to the first one of the first processor electronic modules via the first optical link;

at the first one of the first processor electronic modules: receive the signal via the first optical link and transmit the signal to the third one of the first processor electronic modules via the second optical link; and

at the third one of the first processor electronic modules: receive the signal via the second optical link and perform a second computation based on the signal.

16. An optical link system, comprising:

a photonics substrate;

a plurality of optical links, each optical link of the plurality of optical links comprising:

one of a plurality of optical waveguides defined on the photonics substrate; and

one of a plurality of first optoelectronic transducers optically coupled to the optical waveguide; and/or one of a plurality of second optoelectronic transducers optically coupled to the optical waveguide; and

a plurality of electronics modules, comprising:

a plurality of first processor electronic modules, each first processor electronic module comprising:

a respective first electronics chip or chiplet mounted on the photonics substrate; and

a respective first processor core defined on the respective first electronics chip or chiplet;

a first switch configured for routing flows of data between each one of the plurality of first processor electronic modules and others of the plurality of electronics modules;

wherein the plurality of optical links communicatively couple the plurality of first processor electronic modules to the first switch;

wherein:

the plurality of first electronic processor modules defines a rectangular array comprising a plurality of rows and a plurality of columns;

each row of the plurality of rows comprises a respective subset of at least three of the first processor electronic modules of the plurality of first processor electronic modules, wherein, for each row, each first processor electronic module of the row is communicatively connected directly to every other nearest neighboring first processor electronic module of the row via a respective optical link of the plurality of optical links; and

each column of the plurality of columns comprises a respective subset of at least three of the first processor electronic modules of the plurality of first processor electronic modules, wherein, for each column, each first processor electronic module of the column is communicatively connected directly to every other nearest neighboring first processor electronic module of the column via a respective optical link of the plurality of optical links.

Assignments (2)

Continuity (5)

References Cited (49)