High performance inductive sensing all digital phase locked loop
Front-end circuits that combine inductive and capacitive sensing are described. In one embodiment, an apparatus includes a plurality of inductive elements, an inductive measurement circuit, and a frequency divider circuit. The inductive measurement circuit is to output a first signal with a first frequency. The first signal is associated with an inductance change of one of the inductive elements. A feedback circuit can maintain the sinusoidal operation of the first signal. The frequency divider circuit can generate a second signal with a second frequency that is lower than the first frequency.
1. An apparatus comprising:
an inductance-sensing circuit coupled to a sensor, wherein the inductance-sensing circuit comprises:
a digital phase-frequency detector (PFD) to receive a first signal representing a reference frequency and a second signal representing a second signal representing a sensor frequency;
a first capacitive element;
a second capacitive element, wherein:
the first capacitive element is selectively coupled between the sensor and the digital PFD to make a first adjustment of the sensor frequency
the second capacitive element is selectively coupled between the sensor and the digital PFD to make a second adjustment of the sensor frequency, and
an output of the inductance-sensing circuit represents an inductance change of the sensor;
a proportional integral (PI) controller coupled to the digital PFD, the PI controller to selectively couple the first capacitive element and the digital PFD to make the first adjustment; and
a digital filter coupled to the PI controller, the digital filter to provide the output representing the inductance change.
2. The apparatus of claim 1 , wherein the inductance-sensing circuit further comprises:
a control circuit coupled to the second capacitive element, wherein the control circuit is to receive a digital value that controls an effective capacitance of the second capacitive element.
3. The apparatus of claim 2 , wherein the control circuit is to receive the digital value from the PI controller.
4. The apparatus of claim 1 , wherein the inductance-sensing circuit further comprises a variable capacitance circuit comprising the second capacitive element, wherein the variable capacitance circuit is controlled digitally.
5. The apparatus of claim 1 , further comprising:
a first terminal and a second terminal, wherein the sensor is coupled between the first terminal and the second terminal, wherein the first capacitive element is coupled to the second terminal; and
switching circuitry coupled to the first capacitive element and configured to selectively couple the first capacitive element to the second terminal, wherein the inductance-sensing circuit further comprises
the digital filter; and
a digital phase locked loop (PLL), comprising the digital PFD, coupled to the second terminal, wherein the digital PLL is configured to receive as inputs, the first signal and the second signal, wherein the digital PLL is to output a digital bitstream as a control signal, wherein the switching circuitry is configured to receive the control signal, wherein the digital filter is configured to receive the digital bitstream as an input and to output a digital value as the output of the inductance-sensing circuit, the output representing the inductance change of the sensor.
6. The apparatus of claim 5 , wherein the digital PLL comprises:
the digital PFD coupled to the second terminal and configured to receive the first signal and the second signal; and
a Proportional Integral (PI) controller coupled to an output of the digital PFD, wherein the PI controller is to output the control signal based on the output of the digital PFD.
7. The apparatus of claim 6 , wherein the digital PFD comprises a comparator comprising:
a first input coupled to the first terminal;
a second input coupled to the second terminal, wherein the comparator is configured to receive the first signal as differential inputs; and
a clock input configured to receive the second signal to clock comparisons of the differential inputs.
8. The apparatus of claim 6 , wherein the digital PFD comprises:
a comparator with differential inputs and differential outputs;
a first chop circuit coupled to the first terminal and the second terminal and the differential inputs; and
a second chop circuit coupled to the differential outputs, wherein the first chop circuit and the second chop circuit are clocked by a third signal, wherein the third signal comprises a rate that is a fraction of the reference frequency.
9. The apparatus of claim 1 , further comprising:
a first terminal and a second terminal, wherein the sensor is coupled between the first terminal and the second terminal;
a current source;
a cross-coupled differential transistor pair coupled to the current source, wherein the second capacitive element is coupled to the first terminal; and
switching circuitry coupled to the second capacitive element and configured to selectively couple the second capacitive element to the second terminal.
10. The apparatus of claim 1 , wherein a capacitance of the second capacitive element is programmable.
11. The apparatus of claim 1 , further comprising:
a first terminal and a second terminal, wherein the sensor is coupled between the first terminal and the second terminal;
a current source;
a cross-coupled differential transistor pair coupled to the current source, wherein the second capacitive element is coupled to the first terminal;
a third capacitive element coupled to the second terminal; and
second switching circuitry coupled to the second capacitive element and the third capacitive element, wherein the second switching circuitry comprises:
a first switch coupled between the second capacitive element and a ground potential;
a second switch coupled between the third capacitive element and the ground potential; and
a third switch coupled between the second capacitive element and the third capacitive element.
12. The apparatus of claim 11 , wherein a capacitance of the second capacitive element and a capacitance of the third capacitive element are programmable.
13. A system comprising:
a sensor;
a first capacitive element; and
an integrated circuit comprising a first terminal and a second terminal, wherein the first capacitive element and the sensor are coupled in parallel across the first terminal and the second terminal, wherein the integrated circuit comprises an inductance-sensing circuit coupled to a sensor, wherein the inductance-sensing circuit comprises:
a digital phase-frequency detector (PFD) to receive a first signal representing a reference frequency and a second signal representing a second signal representing a sensor frequency;
the first capacitive element;
a second capacitive element, wherein:
the first capacitive element is selectively coupled between the sensor and the digital PFD to make a first adjustment of the sensor frequency,
the second capacitive element is selectively coupled between the sensor and the digital PFD to make a second adjustment of the sensor frequency, and
an output of the inductance-sensing circuit represents an inductance change of the sensor;
a proportional integral (PI) controller coupled to the digital PFD, the PI controller to selectively couple the first capacitive element and the digital PFD to make the first adjustment; and
a digital filter coupled to the PI controller, the digital filter to provide the output representing the inductance change.
14. The system of claim 13 , further comprising:
switching circuitry coupled to the first capacitive element and configured to selectively couple the first capacitive element to the second terminal, wherein the inductance-sensing circuit further comprises
a digital filter; and
a digital phase locked loop (PLL), comprising the digital PFD, coupled to the second terminal, wherein the digital PLL is configured to receive as inputs, the first signal and the second signal, wherein the digital PLL is to output a digital bitstream as a control signal, wherein the switching circuitry is configured to receive the control signal, wherein the digital filter is configured to receive the digital bitstream as an input and to output a digital value as the output of the inductance-sensing circuit, the output representing the inductance change of the sensor.
15. The system of claim 14 , wherein the digital PLL comprises:
the digital PFD coupled to the second terminal and configured to receive the first signal and the second signal; and
the Proportional Integral (PI) controller coupled to an output of the digital PFD, wherein the PI controller is to output the control signal based on the output of the digital PFD.
16. The system of claim 14 , further comprising:
a current source;
a cross-coupled differential transistor pair coupled to the current source; and
second switching circuitry configured to selectively couple a parallel capacitance across the first terminal and the second terminal, wherein the parallel capacitance is programmable.
17. The system of claim 14 , further comprising:
a current source; and
a cross-coupled differential transistor pair coupled to the current source, wherein the second capacitive element is selectively coupled in parallel with an inductive element of the sensor by the switching circuitry.
18. A method comprising:
measuring, using an inductance-sensing circuit having a digital phase-frequency detector (PFD), a first signal having a sensor frequency of a sensor coupled to the inductance-sensing circuit, wherein the digital PFD receives a second signal representing a reference frequency;
selectively coupling, by a proportional integral (PI) controller coupled to the digital PFD, a first capacitive element between the sensor and the digital PFD to make a first adjustment of the sensor frequency;
selectively coupling a second capacitive element between the sensor and the digital PFD to make a second adjustment of the sensor frequency; and
providing, by a digital filter coupled to the PI controller, an output representing an inductance change of the sensor.