Coding circuit and memory device including the same
View Patent ↗A coding circuit includes an encoder circuit that generates parity by applying input data to a parity generating matrix and generate input codeword by concatenating the input data and the parity, and a decoder circuit that detects and corrects an out-of-boundary 2-bit error using syndromes. The out-of-boundary 2-bit error corresponds to two 1-bit errors occurred at two symbols respectively among a plurality of symbols included in output codeword, and the syndromes are generated by applying the output codeword to the parity generating matrix.
1. A coding circuit comprising:
an encoder circuit configured to generate parity by applying input data to a parity generating matrix and generate input codeword by concatenating the input data and the parity; and
a decoder circuit configured to detect and correct an out-of-boundary 2-bit error using syndromes, the out-of-boundary 2-bit error corresponding to two 1-bit errors occurred at two symbols respectively among a plurality of symbols included in output codeword, the syndromes being generated by applying the output codeword to the parity generating matrix.
2. The coding circuit of claim 1 , wherein the encoder circuit comprises:
a first concatenation circuit configured to concatenate the input data and padding data;
a selection circuit configured to select an output of the first concatenation circuit or the output codeword;
a parity generator configured to apply an output of the selection circuit to the parity generating matrix; and
a second concatenation circuit configured to generate the input codeword by concatenating the input data and an output of the parity generator.
3. The coding circuit of claim 2 , wherein the selection circuit selects the output of the first concatenation circuit during a write operation and selects the output codeword during a read operation and the parity generator generates the syndromes during the read operation.
4. The coding circuit of claim 1 , wherein the decoder circuit includes:
a first error detection circuit configured to detect a 1-symbol error using the syndromes, the 1-symbol error including an error occurred in a single symbol among a plurality of symbols included in the output codeword;
a second error detection circuit configured to detect the out-of-boundary 2-bit error using the syndromes; and
an error correction circuit configured to provide output data by correcting an error in the output codeword based on detection results of the first error detection circuit and the second error detection circuit.
5. The coding circuit of claim 4 , wherein the second error detection circuit includes:
an error value estimation circuit configured to generate an estimated error value by estimating errors based on a first syndrome among the syndromes; and
an error determination circuit configured to provide an error value and an error location by detecting the out-of-boundary 2-bit error based on the estimated error value and a second syndrome among the syndromes.
6. The coding circuit of claim 5 , wherein the error value estimation circuit generates the estimated error value based on the number of a given logic value included in the first syndrome.
7. The coding circuit of claim 6 , wherein the error determination circuit includes:
an error location detection circuit configured to determine a match of the out-of-boundary 2-bit error to a specific type based on the estimated error value and the second syndrome; and
an error decision circuit configured to decide the error location and the error value based on the match.
8. The coding circuit of claim 7 , wherein the type includes a first type corresponding to two 1-bit errors occurring in two data symbols respectively, a second type corresponding to two 1-bit errors occurring in a single data symbol and first parity respectively, and a third type corresponding to two 1-bit errors occurring in a single data symbol and second parity respectively, and
wherein the error location detection circuit includes:
a first error location detection circuit configured to determine whether the out-of-boundary 2-bit error corresponds to the first type;
a second error location detection circuit configured to determine whether the out-of-boundary 2-bit error corresponds to the second type; and
a third error location detection circuit configured to determine whether the out-of-boundary 2-bit error corresponds to the third type.
9. The coding circuit of claim 8 , wherein each of the first and second error location detection circuits generates a plurality of estimated syndromes corresponding to the second syndrome, and compares the second syndrome with the plurality of estimated syndromes and a plurality of calculated values to generate one or more output signals each indicating the match, the plurality of calculated values being stored in a look-up table.
10. The coding circuit of claim 8 , wherein the third error location detection circuit generates a plurality of estimated syndromes corresponding to the second syndrome, and compares the second syndrome with the plurality of estimated syndromes to generate an output signal indicating the match.
11. A memory device comprising:
a memory cell array; and
a coding circuit configured to provide input codeword to the memory cell array by encoding input data, and to generate output data and a detection signal by decoding output codeword output from the memory cell array,
wherein the coding circuit includes:
an encoder circuit configured to generate parity by applying the input data to a parity generating matrix and generate the input codeword by concatenating the input data and the parity; and
a decoder circuit configured to detect and correct an out-of-boundary 2-bit error using syndromes, the out-of-boundary 2-bit error corresponding to two 1-bit errors occurred at two symbols respectively among a plurality of symbols included in the output codeword, the syndromes being generated by applying the output codeword to the parity generating matrix.
12. The memory device of claim 11 , wherein the encoder circuit further comprises:
a first concatenation circuit configured to concatenate the input data and padding data;
a selection circuit configured to select an output of the first concatenation circuit or the output codeword;
a parity generator configured to apply an output of the selection circuit to the parity generating matrix; and
a second concatenation circuit configured to generate the input codeword by concatenating the input data and an output of the parity generator.
13. The memory device of claim 12 , wherein the selection circuit selects the output of the first concatenation circuit during a write operation and selects the output codeword during a read operation and the parity generator generates the syndromes during the read operation.
14. The memory device of claim 11 , wherein the decoder circuit includes:
a first error detection circuit configured to detect a 1-symbol error using the syndromes, the 1-symbol error including an error occurred in a single symbol among a plurality of symbols included in the output codeword;
a second error detection circuit configured to detect the out-of-boundary 2-bit error using the syndromes; and
an error correction circuit configured to provide output data by correcting an error in the output codeword based on detection results of the first error detection circuit and the second error detection circuit.
15. The memory device of claim 14 , wherein the second error detection circuit includes:
an error value estimation circuit configured to generate an estimated error value by estimating errors based on a first syndrome among the syndromes; and
an error determination circuit configured to provide an error value and an error location by detecting the out-of-boundary 2-bit error based on the estimated error value and a second syndrome among the syndromes.
16. The memory device of claim 15 , wherein the error value estimation circuit generates the estimated error value based on the number of a given logic value included in the first syndrome.
17. The memory device of claim 16 , wherein the error determination circuit includes:
an error location detection circuit configured to determine a match of the out-of-boundary 2-bit error to a specific type based on the estimated error value and the second syndrome; and
an error decision circuit configured to decide the error location and the error value based on the match.
18. The memory device of claim 17 , wherein the type includes a first type corresponding to two 1-bit errors occurring in two data symbols respectively, a second type corresponding to two 1-bit errors occurring in a single data symbol and first parity respectively, and a third type corresponding to two 1-bit errors occurring in a single data symbol and second parity respectively, and
wherein the error location detection circuit includes:
a first error location detection circuit configured to determine whether the out-of-boundary 2-bit error corresponds to the first type;
a second error location detection circuit configured to determine whether the out-of-boundary 2-bit error corresponds to the second type; and
a third error location detection circuit configured to determine whether the out-of-boundary 2-bit error corresponds to the third type.
19. The memory device of claim 18 , wherein each of the first and second error location detection circuits generates a plurality of estimated syndromes corresponding to the second syndrome, and compares the second syndrome with the plurality of estimated syndromes and a plurality of calculated values to generate one or more output signals each indicating the match, the plurality of calculated values being stored in a look-up table.
20. The memory device of claim 18 , wherein the third error location detection circuit generates a plurality of estimated syndromes corresponding to the second syndrome, and compares the second syndrome with the plurality of estimated syndromes to generate an output signal indicating the match.