Gate stress test architecture
According to an embodiment, a circuit for transistor gate stress testing is proposed. The circuit includes a first p-channel MOSFET with its drain linked to the transistor's gate; a second p-channel MOSFET coupling its source to the first p-channel MOSFET's source at a node and its drain to a supply voltage; a first n-channel MOSFET with its source to ground and drain to the transistor's gate; a second n-channel MOSFET with its source to ground and drain to the second p-channel MOSFET's gate; a third p-channel MOSFET with its source and drain bridging the node to the second n-channel MOSFET's drain; a fourth p-channel MOSFET in trans-diode setup, its gate to the third p-channel MOSFET's gate and source to the supply rail; plus a current source placed between the fourth p-channel MOSFET's drain and ground.
1 . A circuit for gate stress testing a transistor, the circuit comprising:
a first p-channel metal-oxide-semiconductor field effect transistor (MOSFET), a drain terminal of the first p-channel MOSFET coupled to a gate terminal of the transistor;
a second p-channel MOSFET, a source terminal and a drain terminal of the second p-channel MOSFET coupled to a source terminal of the first p-channel MOSFET at a first node and a supply voltage rail, respectively;
a first n-channel MOSFET, a source terminal and a drain terminal of the first n-channel MOSFET coupled to a reference ground and the gate terminal of the transistor, respectively;
a second n-channel MOSFET, a source terminal and a drain terminal of the second n-channel MOSFET coupled to the reference ground and a gate terminal of the second p-channel MOSFET, respectively;
a third p-channel MOSFET, a source terminal and a drain terminal of the third p-channel MOSFET coupled to the first node and the drain terminal of the second n-channel MOSFET, respectively;
a fourth p-channel MOSFET arranged in a trans-diode configuration, a gate terminal of the third p-channel MOSFET coupled to a gate terminal of the fourth p-channel MOSFET, a source terminal of the fourth p-channel MOSFET coupled to the supply voltage rail; and
a current source arranged between a drain terminal of the fourth p-channel MOSFET and the reference ground.
2 . The circuit of claim 1 , wherein the first, the second, the third, and the fourth p-channel MOSFETs and the first and the second n-channel MOSFETs are enhancement-mode type MOSFETs.
3 . The circuit of claim 1 , wherein gate terminals of the first p-channel MOSFET, the first n-channel MOSFET, and the second n-channel MOSFET are couplable to a control circuitry to adjust a gate voltage at an associated MOSFET.
4 . The circuit of claim 1 , wherein the current source is couplable to a control circuitry to adjust a current sunk through the drain terminal of the fourth p-channel MOSFET to the reference ground.
5 . The circuit of claim 1 , wherein during gate stress testing, the first p-channel MOSFET, the first n-channel MOSFET, and the second n-channel MOSFET are in an OFF state, and wherein during a functional mode of the transistor, the third p-channel MOSFET, the fourth p-channel MOSFET, and the second n-channel MOSFET are in an OFF state and the second p-channel MOSFET is in an ON state.
6 . The circuit of claim 1 , wherein during gate stress testing, the second p-channel MOSFET transitions from an ON state to an OFF state in response to an external voltage being applied to the gate terminal of the transistor that exceeds a voltage at the supply voltage rail.
7 . The circuit of claim 1 , wherein during gate stress testing, the current source is configured to sink a current to generate a source-to-gate voltage to turn ON the third p-channel MOSFET and the fourth p-channel MOSFET.
8 . A DC-DC converter, comprising:
a control circuitry;
a low-side switch; and
a circuit for gate stress testing the low-side switch, the circuit comprising:
a first p-channel metal-oxide-semiconductor field effect transistor (MOSFET), a drain terminal of the first p-channel MOSFET coupled to a gate terminal of the low-side switch;
a second p-channel MOSFET, a source terminal and a drain terminal of the second p-channel MOSFET coupled to a source terminal of the first p-channel MOSFET at a first mode node and a supply voltage rail, respectively;
a first n-channel MOSFET, a source terminal and a drain terminal of the first n-channel MOSFET coupled to a reference ground and the gate terminal of the low-side switch, respectively;
a second n-channel MOSFET, a source terminal and a drain terminal of the second n-channel MOSFET coupled to the reference ground and a gate terminal of the second p-channel MOSFET, respectively;
a third p-channel MOSFET, a source terminal and a drain terminal of the third p-channel MOSFET coupled to the first mode node and the drain terminal of the second n-channel MOSFET, respectively;
a fourth p-channel MOSFET arranged in a trans-diode configuration, a gate terminal of the third p-channel MOSFET coupled to a gate terminal of the fourth p-channel MOSFET, a source terminal of the fourth p-channel MOSFET coupled to the supply voltage rail; and
a current source arranged between a drain terminal of the fourth p-channel MOSFET and the reference ground.
9 . The DC-DC converter of claim 8 , wherein the first, the second, the third, and the fourth p-channel MOSFETs and the first and the second n-channel MOSFETs are enhancement-mode type MOSFETs.
10 . The DC-DC converter of claim 8 , wherein gate terminals of the first p-channel MOSFET, the first n-channel MOSFET, and the second n-channel MOSFET are coupled to the control circuitry, the control circuitry configured to adjust a gate voltage at an associated MOSFET.
11 . The DC-DC converter of claim 8 , wherein the current source is coupled to the control circuitry, the control circuitry configured to adjust a current sunk through the drain terminal of the fourth p-channel MOSFET to the reference ground.
12 . The DC-DC converter of claim 8 , wherein during gate stress testing, the first p-channel MOSFET, the first n-channel MOSFET, and the second n-channel MOSFET are in an OFF state, and wherein during a functional mode of the transistor, the third p-channel MOSFET, the fourth p-channel MOSFET, and the second n-channel MOSFET are in an OFF state and the second p-channel MOSFET is in an ON state.
13 . The DC-DC converter of claim 8 , wherein during gate stress testing, the second p-channel MOSFET transitions from an ON state to an OFF state in response to an external voltage being applied to the gate terminal of the transistor that exceeds a voltage at the supply voltage rail.
14 . The DC-DC converter of claim 8 , wherein during gate stress testing, the current source is configured to sink a current to generate a source-to-gate voltage to turn ON the third p-channel MOSFET and the fourth p-channel MOSFET.
15 . A method for gate stress testing a transistor, the method comprising:
applying a first control signal to a gate terminal of a first p-channel metal-oxide-semiconductor field effect transistor (MOSFET) to deactivate the first p-channel MOSFET, a drain terminal of the first p-channel MOSFET coupled to a gate terminal of the transistor;
applying a second control signal to a gate terminal of a first n-channel MOSFET to deactivate the first n-channel MOSFET, a source terminal and a drain terminal of the first n-channel MOSFET coupled to a reference ground and the gate terminal of the transistor, respectively;
applying a third control signal to a gate terminal of a second n-channel MOSFET to deactivate the second n-channel MOSFET and place the gate terminal of a second p-channel MOSFET as a floating node, a source terminal and a drain terminal of the second n-channel MOSFET coupled to the reference ground and a gate terminal of the second p-channel MOSFET, respectively, and a source terminal and a drain terminal of the second p-channel MOSFET coupled to a source terminal of the first p-channel MOSFET at a first node and a supply voltage rail, respectively;
applying a fourth control signal to a current source to generate a current flow at a drain terminal of a fourth p-channel MOSFET to the reference ground, the fourth p-channel MOSFET arranged in a trans-diode configuration, a gate terminal of a third p-channel MOSFET coupled to a gate terminal of the fourth p-channel MOSFET, a source terminal of the fourth p-channel MOSFET coupled to the supply voltage rail, and a source terminal and a drain terminal of the third p-channel MOSFET coupled to the first node and the drain terminal of the second n-channel MOSFET, respectively; and
applying an external voltage to the transistor to gate stress the transistor, wherein in response to the external voltage exceeding a voltage at the supply voltage rail, the second p-channel MOSFET transitions from an ON state to an OFF state.
16 . The method of claim 15 , wherein the first, the second, the third, and the fourth p-channel MOSFETs and the first and the second n-channel MOSFETs are enhancement-mode type MOSFETs.
17 . The method of claim 15 , wherein during a functional mode of the transistor, the third p-channel MOSFET, the fourth p-channel MOSFET, and the second n-channel MOSFET are in an OFF state and the second p-channel MOSFET is in an ON state.
18 . The method of claim 15 , wherein in response to the current flow at the drain terminal of the fourth p-channel MOSFET exceeding a threshold, the third p-channel MOSFET and the fourth p-channel MOSFET transition from an OFF state to an ON state.
19 . The method of claim 15 , wherein the transistor is a low-side switch of a DC-DC power converter.
20 . The method of claim 19 , further comprising generating the first, second, third, and fourth control signals by a control circuitry of the DC-DC power converter.