TRANSISTOR DEVICE HAVING A CAPACITIVE VOLTAGE DIVIDER CIRCUIT
A transistor device includes: a substrate; an epitaxial layer stack formed on the substrate, the epitaxial layer stack including a heterojunction between two epitaxial layers having different band gaps, the heterojunction defining a channel region of the transistor device; a source terminal electrically connected to a source region of the epitaxial layer stack; a drain terminal electrically connected to a drain region of the epitaxial layer stack; a gate terminal electrically connected to a gate structure laterally between the source region and the drain region; a substrate terminal electrically connected to the substrate; and a capacitive voltage divider circuit electrically connected between the source region and the substrate. In a blocking state of the transistor device, the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value. Additional transistor device embodiments are described.
1 . A transistor device, comprising:
a substrate;
an epitaxial layer stack formed on the substrate, the epitaxial layer stack including a heterojunction between two epitaxial layers having different band gaps, the heterojunction defining a channel region of the transistor device;
a source terminal electrically connected to a source region of the epitaxial layer stack;
a drain terminal electrically connected to a drain region of the epitaxial layer stack;
a gate terminal electrically connected to a gate structure laterally between the source region and the drain region;
a substrate terminal electrically connected to the substrate; and
a capacitive voltage divider circuit electrically connected between the source region and the substrate,
wherein in a blocking state of the transistor device, the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value.
2 . The transistor device of claim 1 , wherein the capacitive voltage divider circuit comprises a voltage clamp device electrically connected from the substrate to the source region in a forward direction.
3 . The transistor device of claim 2 , wherein the voltage clamp device comprises a chain of p-GaN diodes electrically connected in series between the substrate and the source region, wherein an anode of a first one of the p-GaN diodes in the chain is electrically connected to the substrate and a cathode of a last one of the p-GaN diodes in the chain is electrically connected to the source region.
4 . The transistor device of claim 2 , wherein the voltage clamp device comprises a chain of gated GaN diodes electrically connected in series between the substrate and the source region, wherein an anode of a first one of the gated GaN diodes in the chain is electrically connected to the substrate and a cathode of a last one of the gated GaN diodes in the chain is electrically connected to the source region.
5 . The transistor device of claim 2 , wherein the voltage clamp device comprises a chain of p-GaN diodes and gated GaN diodes electrically connected in series between the substrate and the source region, wherein an anode of a first one of the diodes in the chain is electrically connected to the substrate and a cathode of a last one of the diodes in the chain is electrically connected to the source region.
6 . The transistor device of claim 2 , wherein the capacitive voltage divider circuit further comprises a discharge diode device in parallel with the voltage clamp device, and wherein the discharge diode device is configured to discharge a negative potential on the substrate when the transistor device switches from off to on.
7 . The transistor device of claim 6 , wherein the discharge diode device is a gated diode having a source electrically connected to the source region, a drain electrically connected to the substrate, and a gate electrically connected to the source of the gated diode or to the gate terminal.
8 . The transistor device of claim 6 , wherein the discharge diode device is a p-GaN diode having an anode electrically connected to the source region and a cathode electrically connected to the substrate.
9 . The transistor device of claim 2 , wherein the capacitive voltage divider circuit further comprises a capacitor in parallel with the voltage clamp device.
10 . The transistor device of claim 1 , wherein the capacitive voltage divider circuit comprises a capacitor electrically connected between the substrate and the source region.
11 . The transistor device of claim 10 , wherein the capacitive voltage divider circuit further comprises a discharge diode device in parallel with the capacitor, and wherein the discharge diode device is configured to discharge a negative potential on the substrate when the transistor device switches from off to on.
12 . The transistor device of claim 11 , wherein the discharge diode device is a gated diode having a source electrically connected to the source region, a drain electrically connected to the substrate, and a gate electrically connected to the source of the gated diode or to the gate terminal.
13 . The transistor device of claim 11 , wherein the discharge diode device is a p-GaN diode having an anode electrically connected to the source region and a cathode electrically connected to the substrate.
14 . The transistor device of claim 1 , wherein the capacitive voltage divider circuit comprises a discharge diode device electrically connected from the substrate to the source region in a reverse direction, and wherein the discharge diode device is configured to discharge a negative potential on the substrate when the transistor device switches from off to on.
15 . The transistor device of claim 14 , wherein the discharge diode device is a gated diode having a source electrically connected to the source region, a drain electrically connected to the substrate, and a gate electrically connected to the source of the gated diode or to the gate terminal.
16 . The transistor device of claim 14 , wherein the capacitive voltage divider circuit further comprises a first resistor electrically connected between the gate and the source of the gated diode.
17 . The transistor device of claim 16 , wherein the capacitive voltage divider circuit further comprises a second resistor electrically connected between the drain of the gated diode and the drain region.
18 . The transistor device of claim 14 , wherein the discharge diode device is a p-GaN diode having an anode electrically connected to the source region and a cathode electrically connected to the substrate.
19 . The transistor device of claim 1 , wherein the capacitive voltage divider circuit comprises:
a discharge diode device electrically connected from the substrate to the source region in a reverse direction, wherein the discharge diode device is configured to discharge a negative potential on the substrate when the transistor device switches from off to on; and
a voltage clamp device electrically connected between the substrate and a gate of the discharge diode device.
20 . The transistor device of claim 19 , wherein the voltage clamp device comprises a diode having an anode electrically connected to the gate of the discharge diode device and a cathode electrically connected to the substrate.
21 . The transistor device of claim 20 , wherein the anode of the diode and the gate of the discharge diode device are electrically connected to the gate terminal.
22 . The transistor device of claim 19 , wherein the voltage clamp device comprises a capacitor.
23 . The transistor device of claim 22 , wherein the capacitor and the gate of the discharge diode device are electrically connected to the gate terminal.
24 . A transistor device, comprising:
a substrate;
an epitaxial layer stack formed on the substrate, the epitaxial layer stack including a heterojunction between two epitaxial layers having different band gaps, the heterojunction defining a channel of the transistor device;
a source terminal electrically connected to a source region of the epitaxial layer stack;
a drain terminal electrically connected to a drain region of the epitaxial layer stack;
a gate terminal electrically connected to a gate structure laterally between the source region and the drain region;
a substrate terminal electrically connected to the substrate; and
a capacitive voltage divider circuit electrically connected between the source region and the substrate,
wherein the capacitive voltage divider circuit comprises a chain of diodes electrically connected from the substrate to the source region in a forward direction and/or a capacitor electrically connected between the substrate and the source region.
25 . A transistor device, comprising:
a substrate;
an epitaxial layer stack formed on the substrate, the epitaxial layer stack including a heterojunction between two epitaxial layers having different band gaps, the heterojunction defining a channel of the transistor device;
a source terminal electrically connected to a source region of the epitaxial layer stack;
a drain terminal electrically connected to a drain region of the epitaxial layer stack;
a gate terminal electrically connected to a gate structure laterally between the source region and the drain region;
a substrate terminal electrically connected to the substrate; and
a discharge diode device electrically connected from the substrate to the source region in a reverse direction,
wherein the discharge diode device is configured to discharge a negative potential on the substrate when the transistor device switches from off to on.