Semiconductor packages using package in package systems and related methods
Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.
1. A semiconductor package comprising:
a metal layer;
two or more die, each of the two more die coupled to the metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes;
a first interconnect layer coupled at a source of each of the two more die;
a second interconnect layer coupled to a gate of each of the two or more die; and
an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, the metal layer, and the second interconnect layer;
wherein each drain of the two or more die faces towards the metal layer.
2. The package of claim 1 , wherein the encapsulant encapsulates a portion of a gate package contact.
3. The package of claim 2 , wherein the metal layer and the gate package contact are configured to couple with a substrate.
4. The package of claim 1 , wherein the first interconnect layer is configured to couple with a clip and electrically coupled with a substrate through the clip.
5. The package of claim 1 , wherein the second interconnect layer is configured to couple with a clip.
6. The package of claim 1 , wherein the two or more die are power semiconductor die.
7. The package of claim 1 , wherein the two or more die comprise silicon carbide.
8. The package of claim 2 , wherein the metal layer and the gate package contact are comprised in a leadframe.
9. A semiconductor package comprising:
two or more encapsulated die assemblies, each encapsulated die assembly comprising:
two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die;
a first interconnect layer coupled at a source of each of the two more die;
a second interconnect layer electrically coupled to a gate of each of the two or more die; and
an encapsulant surrounding the two or more die and at least a portion of the first interconnect layer, the metal layer, and the second interconnect layer; and
one of a substrate or a leadframe coupled to the two or more encapsulated die assemblies.
10. The package of claim 9 , wherein the one of the substrate or the leadframe is coupled to the two or more encapsulated die assemblies at a drain side of the two or more encapsulated die assemblies.
11. The package of claim 9 , wherein at least three die are electrically coupled in parallel in each of the two or more encapsulated die assemblies.
12. The package of claim 9 , further comprising two or more leads coupled to the one of the substrate or the leadframe.
13. The package of claim 9 , further comprising one or more clips coupled to the one of the substrate or the leadframe.
14. The package of claim 9 , further comprising two or more clips coupled to a source side of the two or more encapsulated die assemblies.
15. The package of claim 9 , wherein the metal layer of the two or more encapsulated die assemblies is comprised in a second leadframe.
16. A method of forming a semiconductor package, the method comprising:
providing two or more die;
coupling each of the two or more die to a metal layer at a drain of each of the two or more die, the two or more die and each metal layer arranged in two parallel planes;
forming a first interconnect layer coupled to a source of each of the two or more die;
encapsulating the two or more die, at least a portion of the first interconnect layer, and at least a portion of the metal layer with an encapsulant using one of a transfer molding or laminating process; and
forming a second interconnect layer coupled to a gate of each of the two or more die;
wherein the drain of each of the two or more die face the metal layer.
17. The method of claim 16 , wherein the semiconductor package comprises a first encapsulated die assembly, the method further comprising forming a second encapsulated die assembly corresponding to the first encapsulated die assembly.
18. The method of claim 17 , further comprising coupling two or more clips to a source side of the first encapsulated die assembly and the second encapsulated die assembly.
19. The method of claim 16 , wherein coupling each of the two or more die to the metal layer further comprises using a silver sintering film and pressure sintering.
20. The method of claim 17 , wherein forming the first encapsulated die assembly and the second encapsulated die assembly further comprises forming one or more vias in the encapsulant using a laser and filling the one or more vias with copper through electroplating.