IP Library Patent Application 18637047
Patent Application
App. No. 18/637,047

BIPOLAR TRANSISTOR

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
18/637,047
Abstract

An electronic device includes a bipolar transistor. A collector of the bipolar transistor is formed by first and second regions. The second region is located between the first region and a base of the bipolar transistor. A conductive element at least partially surrounds and is insulated from the second region. The conductive element is located between the first region and the base.

Claims (41)

1 . A method of manufacturing an electronic device including a bipolar transistor, the method comprising:

forming a collector of the bipolar transistor to include a first region and a second region;

forming a base of bipolar transistor;

wherein the second region is positioned between the first region and the base; and

manufacturing a conductive element insulated from and at least partially surrounding the second region;

wherein the conductive element is located between the first region and the base.

2 . The method according to claim 1 , wherein the conductive element entirely surrounds the second region.

3 . The method according to claim 1 , wherein the conductive element is made of polysilicon.

4 . The method according to claim 1 , further comprising a biasing pad for the bipolar transistor that is electrically coupled to the conductive element.

5 . The method according to claim 1 , further comprising:

forming a first insulating layer in a substrate;

etching a first cavity in the first insulating layer; and

filling the first cavity with a conductive material to form a conductive region.

6 . The method according to claim 5 , further comprising:

forming a second insulating layer covering the conductive region;

forming a second cavity crossing the conductive region to form the conductive element from the conductive region; and

forming a third insulating layer covering exposed lateral walls of the conductive element.

7 . The method according to claim 6 , further comprising:

doping the substrate to form the first region of the collector; and

epitaxially growing semiconductor material in the second cavity from the first portion to form the second region of the collector.

8 . The method according to claim 7 , further comprising:

forming of an insulated-gate field effect transistor;

wherein portions of the insulated-gate field effect transistor are formed during the step of doping the substrate to form the first region.

9 . The method according to claim 6 , further comprising forming the base on the second insulating layer.

10 . The method according to claim 5 , wherein the electronic device comprises a MOSFET transistor inside and on top of a portion of the substrate which includes said bipolar transistor.

11 . An electronic device, comprising:

a bipolar transistor including:

a collector of comprising a first region and a second region;

a base;

wherein the second region is located between the first region and the base; and

a conductive element at least partially surrounding and insulated from the second portion;

wherein the conductive element is located between the first portion and the base.

12 . The electronic device according to claim 11 , wherein the bipolar transistor is of NPN type and wherein the conductive element is configured to be biased by a positive potential.

13 . The electronic device according to claim 12 , wherein the positive potential has an absolute value smaller than 5 V.

14 . The electronic device according to claim 12 , wherein a value of the positive potential is independent from a value applied to the base, to the collector, and to an emitter of the bipolar transistor.

15 . The electronic device according to claim 11 , wherein the bipolar transistor is of PNP type and wherein the conductive element is configured to be biased by a negative potential.

16 . The electronic device according to claim 15 , wherein the negative potential has an absolute value smaller than 5 V.

17 . The electronic device according to claim 15 , wherein a value of the negative potential is independent from a value applied to the base, to the collector, and to an emitter of the bipolar transistor.

18 . The electronic device according to claim 11 , wherein the conductive element entirely surrounds the second region.

19 . The electronic device according to claim 11 , wherein the conductive element is made of polysilicon.

20 . The electronic device according to claim 11 , further comprising a MOSFET transistor inside and on top of a portion of a substrate which includes said bipolar transistor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2024
From: STMICROELECTRONICS (CROLLES 2) SAS
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068165/0426 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2024
From: CHEVALIER, PASCAL; GUITARD, NICOLAS
To: STMICROELECTRONICS (CROLLES 2) SAS
Reel/Frame 067122/0596 →