Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of Forming A Memory Array Comprising Memory Cells Individually Comprising A Transistor And A Capacitor
A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. An access-line pillar extends elevationally through the vertically-alternating tiers. The gate of individual of the transistors in different of the memory-cell tiers comprises a portion of the elevationally-extending access-line pillar. Other embodiments, including method, are disclosed.
1 . A method of forming a memory array, the memory array comprising memory cells individually comprising a transistor and a capacitor, the method comprising:
forming vertically-alternating tiers of insulative material and transistor material; the transistor-material tiers individually comprising a first source/drain region and a second source/drain region having a channel region horizontally there-between;
forming a pair of access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual ones of the channel regions that are in different of the transistor-material tiers, portions of the access-line pillars in the different transistor-material tiers comprising a pair of gates on the opposite sides of the individual ones of the channel regions of individual ones of the transistors in the different transistor-material tiers;
forming a sense line electrically coupled to multiple of the second source/drain regions; and
forming capacitors individually comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to individual ones of the first source/drain regions, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another.
2 . The method of claim 1 comprising forming conductor material that directly electrically couples the pair of access-line pillars together.
3 . The method of claim 2 comprising forming the conductor material above the pair of access-line pillars.
4 . The method of claim 3 comprising forming a horizontal longitudinally-elongated conductive line above and directly electrically coupled to the conductor material of multiple of the pairs of access-line pillars.
5 . The method of claim 1 wherein the channel region is on only one side of individual ones of the gates in a straight-line horizontal cross-section.
6 . The method of claim 1 wherein the access-line pillars extend vertically or within 10° of vertical.
7 . The method of claim 1 wherein all of the channel region is horizontally-oriented for horizontal current flow there-through.
8 . The method of claim 1 wherein the first electrode is directly electrically coupled to the first source/drain region.
9 . The method of claim 1 wherein individual ones of the multiple second source/drain regions are directly electrically coupled to the sense line.
10 . A method of forming a memory array, the memory array comprising memory cells individually comprising a transistor and a capacitor, the method comprising:
forming vertically-alternating tiers of insulative material and transistor material; the transistor-material tiers individually comprising a first source/drain region and a second source/drain region having a channel region horizontally there-between;
forming a pair of access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual ones of the channel regions that are in different of the transistor-material tiers, portions of the access-line pillars in the different transistor-material tiers comprising a pair of gates on the opposite sides of the individual ones of the channel regions of individual ones of the transistors in the different transistor-material tiers;
forming the individual transistors to comprise a gate insulator that is laterally between the gate and the channel region, the gate insulator being laterally between and separating the gate and the first source/drain region from physically contacting one another, the gate insulator being laterally between and separating the gate and the second source/drain region from physically contacting one another;
forming the first and second source/drain regions to each have a vertical side that is directly against both of the channel region and the gate insulator, a greater quantity of each of the vertical sides of the first and second source/drain regions being directly against the gate insulator than is directly against the channel region;
forming a sense line electrically coupled to multiple of the second source/drain regions; and
forming capacitors individually comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to individual ones of the first source/drain regions, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another.
11 . The method of claim 10 comprising forming the pair of access-line pillars to be quadrilateral in a horizontal cross-section.
12 . The method of claim 10 comprising forming the pair of access-line pillars to have at least one straight side in a horizontal cross-section.
13 . The method of claim 10 comprising forming the pair of access-line pillars to have multiple straight sides in a horizontal cross-section.
14 . A method of forming a memory array, the memory array comprising memory cells individually comprising a transistor and a capacitor, the method comprising:
forming vertically-alternating tiers of insulative material and transistor material; the transistor-material tiers individually comprising a first source/drain region and a second source/drain region having a channel region horizontally there-between;
forming a pair of access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual ones of the channel regions that are in different of the transistor-material tiers, portions of the access-line pillars in the different transistor-material tiers comprising a pair of gates on the opposite sides of the individual ones of the channel regions of individual ones of the transistors in the different transistor-material tiers;
forming a sense line electrically coupled to individual ones of multiple of the second source/drain regions along a y-direction;
forming capacitors individually comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to individual ones of the first source/drain regions, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;
forming a conductive strap that is longitudinally-elongated along the y-direction, the conductive strap directly electrically coupling the pair of access-line pillars together; and
forming two conductive lines that are longitudinally-elongated along an x-direction that is orthogonal to the y-direction, one of the two conductive lines directly electrically coupling together a first series of the conductive straps of multiple of the pairs of access-line pillars that alternate relative to one another along the x-direction, the other of the two conductive lines directly electrically coupling together a second series of the conductive straps of multiple of the pairs of access-line pillars that alternate relative to one another and to the first series of the conductive straps along the x-direction.
15 . The method of claim 14 comprising forming the conductive strap to be straight along the y-direction.
16 . The method of claim 14 comprising forming at least one of the two conductive lines be straight along the x-direction.
17 . The method of claim 14 comprising forming each of the two conductive lines be straight along the x-direction.
18 . The method of claim 14 comprising forming each of the two conductive lines to be directly above some of the capacitors.
19 . A method of forming a memory array, the memory array comprising memory cells individually comprising a transistor and a capacitor, the method comprising:
forming vertically-alternating tiers of insulative material and transistor material; the transistor-material tiers individually comprising a first source/drain region and a second source/drain region having a channel region horizontally there-between;
forming a pair of access-line pillars extending elevationally through the vertically-alternating tiers on opposite sides of individual ones of the channel regions that are in different of the transistor-material tiers, portions of the access-line pillars in the different transistor-material tiers comprising a pair of gates on the opposite sides of the individual ones of the channel regions of individual ones of the transistors in the different transistor-material tiers;
forming a sense line electrically coupled to individual ones of multiple of the second source/drain regions;
forming capacitors individually comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to individual ones of the first source/drain regions, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;
forming a conductive strap above the pair of access-line pillars that is longitudinally-elongated and directly electrically couples the pair of access-line pillars together;
forming a conductive line above the conductive strap that is longitudinally-elongated along an x-direction and that directly electrically couples to the conductive strap of multiple of the pairs of access-line pillars; and
forming a conductive line below the conductive line that is above the conductive strap and that is longitudinally-elongated along a y-direction that is orthogonal to the x-direction, the conductive line that is longitudinally-elongated in the y-direction directly electrically coupling together individual ones of the second capacitor electrodes.
20 . The method of claim 19 comprising forming the conductive strap to not be directly above any of the capacitors.