Universal automatic frequency control for multi-channel receivers
Systems and methods for performing automatic frequency control are provided. Instead of relying on individual frequency tuners for each channel of a multi-channel receiver system, the present subject matter uses a single frequency tuner for receiving each channel of the multi-channel receiver system. A locked demodulator may be designated as a reference demodulator and frequency offset values associated with the reference demodulator may be applied to other demodulators of the multi-channel receiver. These frequency offset values may be used by individual demodulators of each channel for correcting corresponding frequency offsets.
1 . A system comprising:
a tuner;
a first demodulator coupled to the tuner;
a second demodulator couple to the tuner; and
at least one processor coupled to the first and second demodulators;
wherein the tuner receives a first and a second signal;
wherein the first demodulator demodulates the first signal;
wherein the second demodulator demodulates the second signal;
wherein the at least one processor determines a first frequency offset for the first demodulator; and
wherein when the second demodulator is unable to lock the second signal, at least one processor applies the first frequency offset to the second demodulator.
2 . The system of claim 1 , wherein the second demodulator demodulates the second signal based on the first frequency offset.
3 . The system of claim 2 , wherein the at least one processor triggers an update signal for updating unlocked demodulators coupled to the tuner if the first demodulator has drifted.
4 . The system of claim 1 , wherein the second demodulator is locked to the second signal, the at least one processor determines that a frequency drift of the second demodulator is greater than a predetermined frequency drift threshold.
5 . The system of claim 4 , wherein the at least one processor calculates a sample frequency offset based on the frequency drift of the second demodulator.
6 . The system of claim 1 , wherein the at least one processor updates phase and an interpolation ratio for the second demodulator based on the sample frequency offset and the first frequency offset.
7 . The system of claim 1 , wherein at least one processor reset the front end bulk search and timing of second order loops.