FLASH-BASED AI ACCELERATOR

1 . A computing apparatus comprising:

a host circuit; and,

a computing device that includes a memory device for facilitating a neural network operation, the computing device configured to:

read weight values from respective non-volatile memory cells in the memory device by biasing the non-volatile memory cells;

perform a multiplication and accumulation calculation on the non-volatile memory cells using the read weight value; and

output a result of the multiplication and calculation to the host system.

2 . The computing apparatus of claim 1 , wherein the host circuit comprises:

a host processor providing instructions to the computing device for transferring data between the host component and the computing device; and

a dynamic random access memory used by the host processor for storing data and program instructions to run the computing apparatus.

3 . The computing apparatus of claim 2 , wherein the computing device further comprises:

a memory controller communicating with the host processor and commanding to retrieve data from the memory device; and

a dynamic random access memory coupled to the memory controller,

wherein the memory device comprises a plurality of computing non-volatile memory components, each computing non-volatile memory component comprising:

an array of non-volatile memory cells;

a word line driving circuitry comprising a plurality of word line driving circuits, the driving circuitry to bias the non-volatile memory cells;

a source line circuitry comprising a plurality of source line circuits, the source line circuitry configured to send input signals to the non-volatile memory cells and receive output signals from the non-volatile memory cells through respective source lines for the multiplication and accumulation calculation operation on the non-volatile memory cells; and

a bit line circuit configured to send input signals to the non-volatile memory cells and receive output signals from the memory cells through respective bit lines for the multiplication and accumulation calculation operation on the non-volatile memory cells.

4 . The computing apparatus of claim 3 , wherein each of the source line circuit and the bit line circuit comprises:

four switching circuits arranged in two pairs, the two pairs being arranged in parallel and each pair of switching circuits having two switching circuits in series;

a driving circuit between the switching circuits of a first pair of the switching circuits;

a sensing circuit between the switching circuits of a second pair of the switching circuits; and

a buffer coupled to the two pairs of switching circuits.

5 . The computing apparatus of claim 4 , wherein the two parallel switching circuits have a first common node coupled to the buffer and a second common node coupled to the nonvolatile memory array.

6 . The computing apparatus of claim 4 , wherein the memory controller is further configured to control operations of the source line circuit and the bit line circuit.

7 . The computing apparatus of claim 3 , said memory controller is further configured to control a two-way data transfer between the source line circuit and the non-volatile memory cells through respective source lines and a two-way data transfer between the bit line circuit and the non-volatile memory cells through respective bit lines.

8 . The computing apparatus of claim 1 , wherein the memory device comprises:

an array of non-volatile memory cells;

a word line driving circuitry to bias the non-volatile memory cells;

a source line driving circuitry configured to ground the memory cells;

a bit line sensing circuitry configured to receive and sense output signals from the memory cells; and

a computing unit coupled to the bit line sensing circuit, wherein the computing unit is configured to perform a multiplication and accumulation calculation using the read weight values from the non-volatile memory cells, wherein the read weight values are represented by digital values.

9 . The computing apparatus of claim 8 , wherein the computing unit is configured to (1) receive input values from a memory controller that is configured to communicate with the host circuit and (2) read weight values from respective non-volatile memory cells to perform the multiplication and accumulation calculation.

10 . The computing apparatus of claim 9 , wherein the weight values from the non-volatile memory cells comprises floating point weight values.

11 . The computing apparatus of claim 10 , wherein said computing apparatus is configured to:

quantize the floating-point weight values according to a predefined quantization method;

program the non-volatile memory cells with quantized weight values, respectively, and

verify the programmed flash memory cells with preset read reference voltages.

12 . The computing apparatus of claim 11 , wherein the computing apparatus is further configured to quantize the floating-point weight values based on a unified mapping range.

13 . The computing apparatus of claim 12 , wherein the computing apparatus is further configured to quantize the floating-point weight values based on a unified number of non-volatile memory cells.

14 . The computing apparatus of claim 1 , wherein the computing device further comprises a computing processor that is located outside the memory device, wherein the computing processor is configured to perform a multiplication and accumulation calculation using the read weight values from the non-volatile memory cells, wherein the read weight values are represented by digital values.

15 . The computing apparatus of claim 14 , wherein the computing apparatus is further configured to:

quantize the floating-point weight values according to a predefined quantization method;

program non-volatile memory cells with quantized weight values, respectively, and

verify the programmed flash memory cells with preset read reference voltages.

16 . The computing apparatus of claim 15 , wherein the computing apparatus is further configured to quantize the floating-point weight values based on a unified mapping range.

17 . The computing apparatus of claim 16 , wherein the computing apparatus is further configured to quantize the floating-point weight values based on a unified number of non-volatile memory cells.

18 . A method, comprising:

receiving AI machine learning analog data from a pre-trained neural network;

quantize the analog data with floating point data based on a unified mapping range;

programming the non-volatile memory cells with quantized data values; and

reading the flash memory cells with read reference voltages.

19 . The method of claim 18 , the read reference voltage is set halfway between a first threshold voltage range of first programmed memory cells and a second threshold voltage range of second programmed memory cells, the second programmed state being adjacent to the first programmed state.

20 . A method, comprising:

receiving AI machine learning analog data from a pre-trained neural network;

quantize the analog data with floating point data based on a unified number of non-volatile memory cells in an array;

programming the non-volatile memory cells with quantized data values; and

reading the flash memory cells with read reference voltages.