IP Library Granted Patent US 12,548,616
Granted Patent B1
US 12,548,616 · App. 18/667,153 · Granted Feb 10, 2026

Common mode shifting of single-ended signals based on linearity analysis

Inventors: Ashwin S.M. (Vaikom, IN); Venkata Mahesh Thorata (Toronto, CA); Anirudha Anil Shelke (Pune, IN); Avinash Ugrappa (Bengaluru, IN); Nikhil Raghavendra Rao (Bengaluru, IN); Jeffin Joy (Thodupuzha, IN)
Assignee: Cadence Design Systems, Inc.
G11C11/4093H03F3/45475H03K19/017509
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Quick Facts
Patent No.
US 12,548,616
App. No.
18/667,153
Granted
Feb 10, 2026
Kind
B1
Abstract

A first circuit receives a single-ended signal and a reference voltage. The first circuit shifts a common mode of the single-ended signal based on a level-shifting current. A preamplifier receives the single-ended signal and the reference voltage from the first circuit and amplifies the single-ended signal to obtain an amplified signal. A decision feedback equalizer (DFE) system receives the amplified signal and the reference voltage from the preamplifier. The DFE system generates a first average signal height of the amplified signal above the reference voltage and a second average signal height of the amplified signal below the reference voltage. A second circuit provides the level-shifting current to the first circuit and adjusts the level-shifting current based on a linearity parameter associated with the amplified signal.

Claims (44)

1 . A receiver comprising:

a first circuit to receive a single-ended signal and a reference voltage and to shift a common mode of the single-ended signal based on a level-shifting current;

a preamplifier coupled to receive the single-ended signal and the reference voltage from the first circuit and to amplify the single-ended signal to obtain an amplified signal;

a decision feedback equalizer (DFE) system coupled to receive the amplified signal and the reference voltage from the preamplifier and to generate a first average signal height of the amplified signal above the reference voltage and a second average signal height of the amplified signal below the reference voltage; and

a second circuit coupled to provide the level-shifting current to the first circuit, the second circuit to adjust the level-shifting current based on a linearity parameter associated with the amplified signal.

2 . The receiver of claim 1 , further comprising logic coupled between the DFE system and the second circuit, wherein the logic is to:

receive, from the DFE system, the first average signal height;

receive, from the DFE system, the second average signal height;

determine a difference between the first average signal height and the second average signal height, wherein the linearity parameter depends on the difference; and

responsive to determining the difference between the first average signal height and the second average signal height is greater than a threshold criterion, provide an indication to the second circuit to adjust a first value of the level-shifting current to a second value of the level-shifting current.

3 . The receiver of claim 2 , wherein the logic comprising a finite state machine (FSM).

4 . The receiver of claim 1 , wherein the first circuit is further to level shift the reference voltage based on the level-shifting current.

5 . The receiver of claim 4 , wherein the first circuit comprising a first linear equalization circuit to level-shift the common mode of the single-ended signal and a second linear equalization circuit to level-shift the reference voltage, wherein the first linear equalization circuit and second linear equalization circuit are the same circuit.

6 . The receiver of claim 1 , wherein the first circuit is further to attenuate at least one of the single-ended signal or the reference voltage to be within an operating range of the preamplifier.

7 . The receiver of claim 1 , wherein the preamplifier is a differential amplifier and the amplified signal is a differential signal.

8 . The receiver of claim 1 , wherein the receiver is located within a dynamic random access memory (DRAM) or within a processing device.

9 . An integrated circuit comprising:

a first circuit to receive a single-ended signal and a reference voltage and to shift a common mode of the single-ended signal and the reference voltage based on a level-shifting current; and

a second circuit coupled to provide the level-shifting current to the first circuit, the second circuit to adjust the level-shifting current based on a linearity parameter.

10 . The integrated circuit of claim 9 , further comprising:

a preamplifier coupled to receive the single-ended signal and the reference voltage from the first circuit and to amplify the single-ended signal to obtain an amplified signal, wherein the linearity parameter is associated with the amplified signal; and

a decision feedback equalizer (DFE) system coupled to receive the amplified signal and the reference voltage from the preamplifier and to generate a first average signal height of the amplified signal above the reference voltage and a second average signal height of the amplified signal below the reference voltage.

11 . The integrated circuit of claim 10 , further comprising logic coupled between the DFE system and the second circuit, wherein the logic is to:

receive, from the DFE system, the first average signal height;

receive, from the DFE system, the second average signal height;

determine a difference between the first average signal height and the second average signal height, wherein the linearity parameter depends on the difference; and

responsive to determining the difference between the first average signal height and the second average signal height is greater than a threshold criterion, provide an indication to the second circuit to adjust a first value of the level-shifting current to a second value of the level-shifting current.

12 . The integrated circuit of claim 10 , wherein the first circuit is further to attenuate at least one of the single-ended signal or the reference voltage to be within an operating range of the preamplifier.

13 . The integrated circuit of claim 9 , wherein the first circuit is further to level shift the reference voltage based on the level-shifting current.

14 . The integrated circuit of claim 13 , wherein the first circuit comprising a first linear equalization circuit to level-shift the common mode of the single-ended signal and a second linear equalization circuit to level-shift the reference voltage, wherein the first linear equalization circuit and second linear equalization circuit are the same circuit.

15 . The integrated circuit of claim 10 , wherein the preamplifier is a differential amplifier and the amplified signal is a differential signal.

16 . A method of adjusting a single-ended signal of a receiver, the method comprising:

receiving the single-ended signal and a reference voltage;

amplifying the single-ended to obtain an amplified signal;

adjusting a level-shifting current based on a linearity parameter associated with the amplified signal; and

shifting a common mode of the single-ended signal based on the level-shifting current.

17 . The method of claim 16 , further comprising:

determining a first average signal height of the amplified signal below the reference voltage;

determining a second average signal height of the amplified signal above the reference voltage;

determining a difference between the first average signal height and the second average signal height, wherein the linearity parameter depends on the difference; and

responsive to determining the difference between the first average signal height and the second average signal height is greater than a threshold criterion, adjusting a first value of the level-shifting current to a second value of the level-shifting current.

18 . The method of claim 16 , further comprising shifting the reference voltage based on the level-shifting current.

19 . The method of claim 16 , further comprising attenuating at least one of the single-ended signal or the reference voltage to be within an operating range of a preamplifier associated with the receiver.

20 . The method of claim 16 , wherein the receiver is located within a dynamic random access memory (DRAM) or within a processing device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2024
From: S.M., ASHWIN; THORATA, VENKATA MAHESH; SHELKE, ANIRUDHA ANIL; UGRAPPA, AVINASH; RAO, NIKHIL RAGHAVENDRA; JOY, JEFFIN
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 067742/0926 →
Continuity (1)
Provisional Application 63502801 · May 17, 2023
References Cited (2)
US 9973355B1 · Cartina · 2018 [cited by examiner]
US 20150091631A1 · Yildirim · 2015 [cited by examiner]