INTEGRATED CIRCUIT CHIP COMPRISING A RADIOFREQUENCY COMPONENT
The present description concerns an integrated circuit chip including a semiconductor substrate and a radiofrequency component arranged inside and on top of an active region of the semiconductor substrate. The semiconductor substrate includes an amorphous buried layer in contact, by its upper surface, with a lower surface of the active region of the semiconductor substrate.
1 . An integrated circuit chip comprising:
a semiconductor substrate; and
a radiofrequency component arranged inside and on top of an active region of the semiconductor substrate, the semiconductor substrate comprising an amorphous buried layer in contact, by its upper surface, with a lower surface of the active region of the semiconductor substrate.
2 . The chip according to claim 1 , wherein the radiofrequency component is a component intended to receive AC electric signals at frequencies within the range from 3 kHz to 30 GHz.
3 . The chip according to claim 1 , wherein the active region is flush, by its upper surface, with a first surface of the semiconductor substrate.
4 . The chip according to claim 3 , further comprising an interconnection network in contact with the first surface of the semiconductor substrate.
5 . The chip according to claim 1 , wherein the active region is laterally delimited by insulating structures.
6 . The chip according to claim 5 , wherein the insulating structures are insulating trenches.
7 . The chip according to claim 5 , wherein the insulating structures correspond to an assembly of a plurality of laterally-appended doped regions laterally with alternating doping types.
8 . The chip according to claim 5 , wherein the amorphous buried layer is in contact with the insulating structures.
9 . The chip according to claim 1 , wherein the radiofrequency component is a MOS transistor.
10 . A method of manufacturing an integrated circuit chip, the method comprising:
forming a radiofrequency component inside and on top of an active region of a semiconductor substrate; and
forming, in the semiconductor substrate, an amorphous buried layer in contact, by its upper surface, with a lower surface of the active region of the semiconductor substrate.
11 . The method according to claim 10 , wherein the forming of the amorphous buried layer is carried out by ion implantation.
12 . The method according to claim 11 , wherein the forming of the amorphous buried layer is carried out from a first surface of the semiconductor substrate, before the forming of an interconnection network on the first surface of the semiconductor substrate.
13 . The method according to claim 11 , wherein the forming of the amorphous buried layer is carried out after the forming of an interconnection network on a first surface of the semiconductor substrate, the forming of the amorphous buried layer being carried out from a second surface of the semiconductor substrate, opposite to the first surface.
14 . The method according to claim 13 , further comprising thinning of the semiconductor substrate from its second surface, after the forming of the interconnection network and before the step of forming of the amorphous buried layer.
15 . A method of manufacturing an integrated circuit chip, the method comprising:
forming a radiofrequency (RF) component at a first side of a semiconductor substrate, the semiconductor substrate comprising the first side and an opposite second side, the RF component comprising a device region and a trench isolation region laterally surrounding the device region;
thinning the semiconductor substrate from the second side to form a thinned substrate; and
locally forming a buried isolation layer by ion implantation, the buried isolation layer aligned with the trench isolation region.
16 . The method of claim 15 , wherein forming the trench isolation region comprises forming a shallow trench isolation comprising a dielectric material.
17 . The method of claim 15 , wherein forming the trench isolation region comprises forming a plurality of doped regions having opposite doping types.
18 . The method of claim 15 , further comprising forming an interconnection network before the thinning.
19 . The method of claim 15 , further comprising forming insulating structures disposed around the trench isolation region, the insulating structures extending deeper into the substrate than the trench isolation region.
20 . The method of claim 19 , the insulating structures corresponding to an assembly of a plurality of laterally-appended doped regions laterally with alternating doping type.
21 . The method of claim 19 , wherein the buried isolation layer is in contact with the insulating structures.