Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
View Patent ↗Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
1 . An apparatus comprising:
a controller configured to:
provide a first mode register write command to a memory to write a first value for a duty cycle monitoring (DCM) start/stop opcode to cause the memory to perform a first DCM operation; and
provide a second mode register write command to the memory to write a flip bit value for a DCM flip opcode to cause the memory to flip an input for a duty cycle monitor of the memory and perform a second DCM operation.
2 . The apparatus of claim 1 , wherein the controller is further configured to provide a third mode register write command to the memory to write a third value for the DCM start/stop opcode to cause the memory to terminate the DCM operation.
3 . The apparatus of claim 1 , wherein the controller is further configured to issue a mode register read command to read a result of the DCM operation.
4 . The apparatus of claim 3 , wherein the result comprises four bits.
5 . The apparatus of claim 4 , wherein two of the bits are associated with the first DCM operation and two of the bits are associated with the second DCM operation.
6 . The apparatus of claim 1 , wherein the controller is further configured to wait for the memory to complete the first DCM operation prior to providing the second mode register write command.
7 . The apparatus of claim 1 , wherein the controller is configured to update a frequency set point setting of the memory prior to providing the first mode register write command.
8 . The apparatus of claim 1 , wherein the controller is configured to activate a write clock signal prior to providing the first mode register write command.
9 . A system comprising:
a memory comprising:
a mode register configured to store a plurality of opcodes; and
a duty cycle monitor (DCM) configured to perform a DCM operation; and
a controller coupled to the memory, the controller configured to:
cause a first value or a second value to be written to a start/stop opcode of the plurality of opcodes, wherein the DCM operation is started responsive to the first value and the DCM operation is terminated responsive to the second value.
10 . The system of claim 9 , wherein the controller is further configured to cause a ‘1’ or a ‘0’ to be written to a flip bit of the plurality of opcodes.
11 . The system of claim 10 , wherein a first input is provided to the DCM when the flip bit is ‘0’ and a second input is provided to the DCM when the flip bit is ‘1’.
12 . The system of claim 10 , wherein writing the ‘1’ or the ‘0’ to the flip bit causes the memory to automatically capture results of the DCM operation, store the results of the DCM operation in the mode register, reset and restart the DCM.
13 . The system of claim 9 , wherein the controller is further configured to provide a data clock signal to the memory.
14 . The system of claim 9 , wherein the memory comprises a low power double data rate dynamic random access memory.
15 . The system of claim 9 , further comprising a plurality of memories, wherein the memory is included in the plurality of memories, and the controller is coupled to the plurality of memories and configured to provide commands and receive DCM operation results from the plurality of memories.
16 . A method comprising:
providing with a controller, a system clock signal to a plurality of memories;
providing with the controller, a data clock signal to the plurality of memories;
issuing from the controller to at least one memory of the plurality of memories, a first mode register write command to write a first value for a duty cycle monitoring (DCM) start/stop opcode in a mode register of the at least one memory; and
performing with the at least one memory a first DCM operation.
17 . The method of claim 16 , wherein the data clock signal is toggling at a full-rate prior to the first DCM operation.
18 . The method of claim 16 , further comprising:
issuing from the controller a second mode register write command to the at least one memory to write a flip bit value for a DCM flip opcode in the mode register of the memory;
flipping an input for a duty cycle monitor of the memory responsive to writing the flip bit; and
performing with the at least one memory a second DCM operation responsive to writing the flip bit.
19 . The method of claim 18 , further comprising:
issuing from the controller to the at least one memory a mode register read command; and
providing from the at least one memory a result of the first DCM operation, a result of the second DCM operation, or both.
20 . The method of claim 18 , further responsive to writing the flip bit:
automatically capturing with the at least one memory results of the first DCM operation; and
automatically storing the results in the mode register.
21 . The method of claim 18 , further responsive to writing the flip bit, automatically resetting the DCM.
22 . The method of claim 18 , further responsive to writing the flip bit, automatically restarting the DCM.
23 . The method of claim 18 , wherein the first DCM operation is completed prior to issuing the second mode register write command.
24 . The method of claim 16 , further comprising providing from the controller a second mode register write command to the at least one memory to write a third value for the DCM start/stop opcode; and
terminating the first DCM operation responsive to writing the third value.