Memory with virtual page size
View Patent ↗Methods, systems, and devices for memory with a virtual page size are described. Memory cells may be accessed in portions or page sizes that are tailored to a particular use or application. A variable page size may be defined that represents a subset or superset of memory cells in a nominal page size for the array. For example, memory cells associated with a page size of a memory array may be accessed with commands to a memory array. Each command may contain a particular addressing scheme based on the page size of the memory array and may activate one or more sets of memory cells within the array. The addressing scheme may be modified based on the page size of the memory array. Upon activating a desired set of memory cells, one or more individual activated cells may be accessed.
1 . A method, comprising:
receiving a request for data, the request associated with a first quantity of memory cells corresponding to a nominal page size of a memory array;
activating a second quantity of memory cells comprising the requested data based at least in part on receiving the request, the second quantity of memory cells corresponding to a virtual page size of the memory array that is greater than the nominal page size of the memory array;
reading a first subset of the requested data from a first subset of the second quantity of activated memory cells; and
reading, after reading the first subset of the requested data, a second subset of the requested data from a second subset of the second quantity of activated memory cells.
2 . The method of claim 1 , wherein a word line associated with the second quantity of activated memory cells remains activated while the first subset of the second quantity of activated memory cells and the second subset of the second quantity of activated memory cells are accessed.
3 . The method of claim 1 , wherein reading the first subset of the requested data is based at least in part on a first read command and reading the second subset of the requested data is based at least in part on a second read command.
4 . The method of claim 3 , wherein the first subset of the requested data is read after a first duration relative to receiving the first read command and the second subset of the requested data is read after a second duration relative to receiving the second read command.
5 . The method of claim 4 , wherein the first duration corresponds to one or more clock cycles after receiving the first read command and the second duration corresponds to one or more clock cycles after receiving the second read command.
6 . The method of claim 1 , further comprising:
receiving a command to use the nominal page size, wherein the second quantity of memory cells is activated in response to receiving the command.
7 . The method of claim 6 , wherein the request for data comprises the command to use the nominal page size.
8 . The method of claim 6 , further comprising:
receiving the command to use the nominal page size from a host that is coupled with the memory array.
9 . A memory system, comprising:
one or more memory arrays, wherein each respective memory array of the one or more memory arrays includes a plurality of row access lines that are each coupled with a row of memory cells of the respective memory array and a plurality of column access lines that are each coupled with a column of memory cells of the respective memory array; and
one or more memory controllers coupled with the plurality of row access lines and the plurality of column access lines, wherein the one or more memory controllers are operable to:
receive a request for data, the request associated with a first quantity of memory cells corresponding to a nominal page size of a memory array;
activate a second quantity of memory cells comprising the requested data based at least in part on receiving the request, the second quantity of memory cells corresponding to a virtual page size of the memory array that is greater than the nominal page size of the memory array;
read a first subset of the requested data from a first subset of the second quantity of activated memory cells; and
read, after reading the first subset of the requested data, a second subset of the requested data from a second subset of the second quantity of activated memory cells.
10 . The memory system of claim 9 , wherein a word line associated with the second quantity of activated memory cells remains continuously activated while the first subset of the second quantity of activated memory cells and the second subset of the second quantity of activated memory cells are accessed.
11 . The memory system of claim 9 , wherein reading the first subset of the requested data is based at least in part on a first read command and reading the second subset of the requested data is based at least in part on a second read command.
12 . The memory system of claim 11 , wherein the first subset of the requested data is read after a first duration relative to receiving the first read command and the second subset of the requested data is read after a second duration relative to receiving the second read command.
13 . The memory system of claim 12 , wherein the first duration corresponds to one or more clock cycles after receiving the first read command and the second duration corresponds to one or more clock cycles after receiving the second read command.
14 . The memory system of claim 9 , wherein the one or more memory controllers are further operable to:
receive a command to use the nominal page size, wherein the second quantity of memory cells is activated in response to receiving the command.
15 . The memory system of claim 14 , wherein the request for data comprises the command to use the nominal page size.
16 . A memory system, comprising:
one or more memory arrays, wherein each respective memory array of the one or more memory arrays includes a plurality of row access lines that are each coupled with a row of memory cells of the respective memory array and a plurality of column access lines that are each coupled with a column of memory cells of the respective memory array; and
one or more memory controllers coupled with the plurality of row access lines and the plurality of column access lines, wherein the one or more memory controllers are operable to:
receive, from a host device, a request for data, the request for data associated with a page size corresponding to a first quantity of memory cells;
activate a set of memory cells based at least in part on the request for data;
access, based at least in part on activating the set of memory cells, a first subset of the activated set of memory cells, wherein the first subset comprises the first quantity of memory cells; and
access a second subset of the activated set of memory cells, wherein the second subset comprises the first quantity of memory cells, wherein accessing the first subset and the second subset comprises:
reading the first subset of the requested data from the first subset of the activated set of memory cells based at least in part on receiving the request for data; and
reading the second subset of the requested data from the second subset of the activated set of memory cells based at least in part on receiving the request for data.
17 . The memory system of claim 16 , wherein the activated set of memory cells comprises a second quantity of memory cells that is an integer multiple of the first quantity of memory cells.
18 . The memory system of claim 16 , wherein the page size associated with the first quantity of memory cells corresponds to at least one of the rows of memory cells and at least one of the columns of memory cells.
19 . The memory system of claim 18 , wherein the one or more memory controllers are operable to:
access at least one of the row of memory cells based at least in part on accessing the first subset of the activated set of memory cells or accessing the second subset of the activated set of memory cells.
20 . The memory system of claim 16 , further comprising:
a plurality of sense components and a plurality of switches, wherein the one or more memory controllers are operable to:
activate at least one switch of the plurality of switches to access each of the plurality of row access lines and the plurality of column access lines with a sense component of the plurality of sense components; and
access the first subset and the second subset of the activated set of memory cells based at least in part on activating the at least one switch of the plurality of switches.