IP Library Granted Patent US 12,581,145
Granted Patent B2
US 12,581,145 · App. 18/680,033 · Granted Mar 17, 2026

Systems, methods, and devices for video stream synchronization

Inventors: Ying Xiong (Dalian, CN); Hung Pan Ng (Hong Kong, HK); Rongbin Qiu (Shanghai, CN)
Assignee: Infineon Technologies Americas Corp.
H04N21/242H04N5/0675H04N21/4305
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Quick Facts
Patent No.
US 12,581,145
App. No.
18/680,033
Granted
Mar 17, 2026
Kind
B2
Abstract

Systems, methods, and devices perform synchronization operations for video streams. Methods include receiving a video frame at a frame capture unit, the video frame being included in a stream of video data, buffering the video frame using a buffer coupled between the frame capture unit and a frame display unit, and determining an offset value based, at least in part, on a refresh rate associated with the frame capture uni. Methods further include reading, using the frame display unit, the video frame from the buffer after a designated period of time defined by the offset value.

Claims (48)

1 . A method comprising:

receiving a video frame at a frame capture unit, the video frame being included in a stream of video data;

buffering the video frame using a buffer coupled between the frame capture unit and a frame display unit;

determining an offset value based, at least in part, on a refresh rate associated with the frame capture unit; and

reading, using the frame display unit, the video frame from the buffer after a designated period of time defined by the offset value.

2 . The method of claim 1 further comprising:

synchronizing a pixel clock of the frame capture unit and the frame display unit.

3 . The method of claim 1 , wherein the buffering further comprises:

writing, using the frame capture unit, the video frame to a plurality of lines of the buffer.

4 . The method of claim 1 further comprising:

performing a compensation operation to update the offset value.

5 . The method of claim 1 , wherein a size of a video input of the frame capture unit is smaller than a size of a video output of the frame display unit.

6 . The method of claim 5 further comprising:

determining the offset value based on a plurality of reference values.

7 . The method of claim 1 , wherein a number of channels included in a video input of the frame capture unit is smaller than a number of channels included in a video output of the frame display unit.

8 . The method of claim 7 further comprising:

determining the offset value based on a first plurality of reference values; and

determining an additional offset value based on a second plurality of reference values.

9 . The method of claim 1 , wherein the stream of video data comprises augmented reality video data.

10 . A system comprising:

a memory device comprising a buffer, the buffer being configured to buffer video data; and

a processing device comprising a frame capture unit and a frame display unit, the processing device configured to:

receive a video frame at the frame capture unit, the video frame being included in a stream of video data;

determine an offset value based, at least in part, on a refresh rate associated with the frame capture unit; and

read, using the frame display unit, the video frame from the buffer after a designated period of time defined by the offset value.

11 . The system of claim 10 , wherein the processing device is further configured to:

synchronize a pixel clock of the frame capture unit and the frame display unit.

12 . The system of claim 10 , wherein a size of a video input of the frame capture unit is smaller than a size of a video output of the frame display unit.

13 . The system of claim 12 , wherein the processing device is further configured to:

determine the offset value based on a plurality of reference values.

14 . The system of claim 10 , wherein a number of channels included in a video input of the frame capture unit is smaller than a number of channels included in a video output of the frame display unit.

15 . The system of claim 14 , wherein the processing device is further configured to:

determine the offset value based on a first plurality of reference values; and

determine an additional offset value based on a second plurality of reference values.

16 . A device comprising:

processing elements configured to:

receive a video frame at the frame capture unit, the video frame being included in a stream of video data;

buffer the video frame using a buffer coupled between the frame capture unit and a frame display unit;

determine an offset value based, at least in part, on a refresh rate associated with the frame capture unit; and

read, using the frame display unit, the video frame from the buffer after a designated period of time defined by the offset value.

17 . The device of claim 16 , wherein the processing elements are further configured to:

synchronize a pixel clock of the frame capture unit and the frame display unit.

18 . The device of claim 16 , wherein a size of a video input of the frame capture unit is smaller than a size of a video output of the frame display unit, and wherein the processing elements are further configured to:

determine the offset value based on a plurality of reference values.

19 . The device of claim 16 , wherein a number of channels included in a video input of the frame capture unit is smaller than a number of channels included in a video output of the frame display unit.

20 . The device of claim 19 , wherein the processing elements are further configured to:

determine the offset value based on a first plurality of reference values; and

determine an additional offset value based on a second plurality of reference values.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Oct 21, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION; INFINEON TECHNOLOGIES AMERICAS CORP.
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073140/0554 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2025
From: XIONG, YING; NG, HUNG PAN; QIU, RONGBIN
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 070136/0033 →
Continuity (1)
Related Publication 20250373871A1 · Dec 4, 2025
References Cited (3)
US 20060044289A1 · Yee · 2006 [cited by examiner]
US 20140168243A1 · Huang · 2014 [cited by examiner]
US 20210225320A1 · Sin · 2021 [cited by examiner]