DRAM MEMORY DEVICE USING A MECHANISM FOR ROW HAMMER MANAGEMENT

1 . A DRAM memory device which comprises:

at least one DRAM memory bank provided with n memory rows, referred to as row i for i ranging from 1 to n, each row i being liable to effect a row hammer having a range p on one or more rows j, said to be within the hammering range of row i, with j ranging from i+1 to i+p and from i−1 to i−p, each row i being configured to have activation cycles N imposed on it continuously, an activation cycle N comprising an activation A N , of duration T AN , and a preload P N , of duration T PN , preceding the activation A N ;

a logic block for preventing the hammer effect which comprises counting means implementing m hammer counters, called counters k, k ranging from 1 to m, each k counter being associated with one or more of the rows i, and is configured to increment, after the end of each activation cycle N of one or more of the rows i with which it is associated, a count k by an increment value k N , the increment value k being a decreasing function of the duration T PN and also a function of the duration T AN , the increment value k N quantifying the hammer effect from the one or more of the rows i on rows j within hammering range;

a row refresh logic block configured to refresh one or more rows as soon as a count k of one of the associated counters k reaches a threshold value M, the threshold value M being chosen to prevent the row hammer effect.

2 . The device according to claim 1 , wherein the increment value k N is an increasing function of the time T AN ,

3 . The device according to claim 1 , wherein, the count k is incremented by the increment value k N only after the end of the preload P N+1 of the activation cycle N+1 immediately following the activation A N of the activation cycle N, the increment value k N also being a decreasing function of a duration T P(N+1) of the preload P N+1 .

4 . The device according to claim 1 , wherein the set of counters k are saved in at least one table.

5 . The device according to claim 1 , wherein the logic block for preventing the row hammer effect is configured to measure, for each activation cycle N, the duration T AN of each activation A N , and the duration T PN of each preload PN.

6 . The device according to claim 1 , wherein the at least one DRAM memory bank forms a memory bank divided into p sub-banks, each sub-bank h, for h ranging from 1 to p, forming contiguous sections of rows of the memory bank, the number m of counters k is equal to the number p of sub-banks h such that each counter k, for k ranging from 1 to p, is associated with a sub-bank h of its own, for h ranging from 1 to p.

7 . The device according to claim 6 , wherein the logic block for preventing the hammer effect is configured to reset or decrement the counter k associated with a sub-bank h as soon as at least one row of said sub-bank k has been refreshed.

8 . The device according to claim 1 , wherein the number m of counters k is equal to the number n of memory rows, so that each counter k, for k ranging from 1 to n, is associated with a row i, for i ranging from 1 to n, which is its own.

9 . The device according to claim 8 , wherein the refresh logic block is also configured to reset or decrement the counter k as soon as the row, or one of the rows, associated with this counter has been refreshed.

10 . The device according to claim 1 , wherein the refresh logic block is also configured to perform periodic refreshes of the memory row set at regular time intervals.

11 . The device according to claim 1 , wherein he increment value k N is the sum of a first increment value and a second increment value, the first increment value being a function of a delay between activation N−1 of the activation cycle N−1 and activation N of the activation cycle N, the second increment value characterizing the activation duration T AN , of the activation cycle N.

12 . The device according to claim 11 , wherein the determination of the first value and second value involves a first table and a second table, respectively.

13 . A method for preventing the memory row hammer effect of a DRAM device, the DRAM device comprising at least one DRAM memory bank provided with n memory rows called row i for i ranging from 1 to n, the method comprising the implementation of an algorithm for preventing the row hammer effect, said algorithm implementing:

-m hammer counters, called counters k, k ranging from 1 to m, each k counter being associated with one or more of the rows i, and is configured to increment, after the end of each activation cycle N of one or more of the rows i with which it is associated, a count k by an increment value k N , the increment value k N being a decreasing function of the duration T PN and also a function of the duration T AN , the increment value k N quantifying the hammer effect from the one or more of the rows i on rows j within hammering range;

a row refresh logic block configured to refresh one or more rows as soon as a count k of one of the associated counters k reaches a threshold value M, the threshold value M being chosen to prevent the row hammer effect.

14 . The method for preventing the row hammer effect according to claim 13 , wherein the increment value k N is an increasing function of the duration T AN .

15 . The method for preventing the row hammer effect according to claim 14 , wherein the algorithm implements the following steps:

A. Determining the duration T PN ;

B. Determining the duration T AN ;

C. On the basis of the durations T PN and T AN , determining an increment value k N of a counter k associated with row i;

D. Incrementing the counter k by the increment value k N ;

E. Refreshing one or more rows i as soon as the count k of the counter k associated with said one or more rows i reaches the threshold value M.

F. A step, following step E., for decrementing or resetting the count k of the counter k in question.