IP Library Granted Patent US 12,468,480
Granted Patent B2
US 12,468,480 · App. 18/731,089 · Granted Nov 11, 2025

Alleviating interconnect traffic in a disaggregated memory system

Inventors: Vamsee Reddy Kommareddy (Orlando, FL); SeyedMohammad SeyedzadehDelcheh (Sammamish, WA); Sergey Blagodurov (Bellevue, WA)
Assignee: Advanced Micro Devices, Inc.
G06F3/0655G06F3/0602G06F3/065G06F3/0653G06F9/5027G06F12/0802G06F2212/60
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,468,480
App. No.
18/731,089
Granted
Nov 11, 2025
Kind
B2
Abstract

One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a cache memory of a computing node in the disaggregated memory system executing one or more tasks of a host application is initiated based on the write accesses to the fabric-attached memory module.

Claims (32)

1 . A system comprising:

a processor of a computing node configured to:

send read and write accesses to a fabric-attached memory via a fabric interconnect of a disaggregated memory system; and

transfer, based on the read and write accesses, one or more tasks accessing the fabric-attached memory to a processor of a routing system associated with the fabric-attached memory and at least one additional fabric-attached memory via the fabric interconnect.

2 . The system of claim 1 , wherein the transfer is further based on a number of tasks accessing the fabric-attached memory, a total read traffic to the fabric-attached memory, a total write traffic to the fabric-attached memory, a number of the read and write accesses to the fabric-attached memory, or a frequency of the read and write accesses to the fabric-attached memory.

3 . The system of claim 1 , wherein the transfer is initiated in response to an indication that the read and write accesses satisfy a rule.

4 . The system of claim 3 , wherein the rule includes a total read and write traffic to the fabric-attached memory over a duration of time exceeding a threshold amount, the threshold amount being a percentage of a total read and write traffic to the fabric-attached memory and at least one additional fabric-attached memory coupled to the routing system.

5 . The system of claim 4 , wherein the duration of time is a configurable parameter.

6 . The system of claim 4 , wherein the duration of time is a rolling window.

7 . The system of claim 3 , wherein the rule includes a total read and write traffic to the fabric-attached memory and at least one additional fabric-attached memory coupled to the routing system over a duration of time exceeding a threshold amount, the threshold amount being a percentage of a total read and write traffic to multiple fabric-attached memories coupled to the routing system.

8 . The system of claim 3 , wherein the transfer is ceased in response to an indication that the read and write accesses no longer satisfy the rule.

9 . The system of claim 8 , wherein the rule includes:

a first threshold amount to determine that the read and write accesses satisfy the rule; and

a second threshold amount to determine that the read and write accesses no longer satisfy the rule, the second threshold amount being different than the first threshold amount.

10 . The system of claim 1 , wherein the one or more tasks include one or more threads of a host application running in the disaggregated memory system.

11 . The system of claim 1 , wherein the one or more tasks include each task of a host application running in the disaggregated memory system that read from or write to the fabric-attached memory.

12 . The system of claim 1 , wherein the processor is further configured to receive, based on write accesses to the fabric-attached memory, a replicated memory of the fabric-attached memory to a cache memory of the computing node.

13 . A system comprising:

a router configured to:

receive, from a processor of a computing node, read and write accesses to a fabric-attached memory via a fabric interconnect of a disaggregated memory system; and

receive, based on the read and write accesses, an offloading of one or more tasks accessing the fabric-attached memory from the processor of the computing node to an additional processor communicatively coupled to the router within a routing system, the additional processor communicatively coupled to the fabric-attached memory and at least one additional fabric-attached memory via the fabric interconnect.

14 . The system of claim 13 , wherein the offloading is further based on a number of tasks accessing the fabric-attached memory, a total read traffic to the fabric-attached memory, a total write traffic to the fabric-attached memory, a number of the read and write accesses to the fabric-attached memory, or a frequency of the read and write accesses to the fabric-attached memory.

15 . The system of claim 13 , wherein the offloading is initiated in response to a determination that the read and write accesses satisfy a rule.

16 . The system of claim 15 , wherein the rule includes a total read and write traffic to the fabric-attached memory and at least one additional fabric-attached memory coupled to the routing system over a duration of time exceeding a threshold amount, the threshold amount being a percentage of a total read and write traffic to multiple fabric-attached memories coupled to the routing system.

17 . The system of claim 15 , wherein the offloading is ceased in response to an indication that the read and write accesses no longer satisfy the rule.

18 . The system of claim 17 , wherein the rule includes:

a first threshold amount to determine that the read and write accesses satisfy the rule; and

a second threshold amount to determine that the read and write accesses no longer satisfy the rule, the second threshold amount being different than the first threshold amount.

19 . A method comprising:

receiving, based on read and write accesses to a fabric-attached memory via a fabric interconnect of a disaggregated memory system, an indication to offload one or more tasks; and

transferring, in response to the indication, one or more tasks accessing the fabric-attached memory from a processor of a computing node to an additional processor of a routing system associated with the fabric-attached memory via the fabric interconnect, the additional processor communicatively coupled to the fabric-attached memory and at least one additional fabric-attached memory.

20 . The method of claim 19 , wherein the indication is further based on a number of tasks accessing the fabric-attached memory, a total read traffic to the fabric-attached memory, a total write traffic to the fabric-attached memory, a number of the read and write accesses to the fabric-attached memory, or a frequency of the read and write accesses to the fabric-attached memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2024
From: KOMMAREDDY, VAMSEE REDDY; SEYEDZADEHDELCHEH, SEYEDMOHAMMAD; BLAGODUROV, SERGEY
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 068038/0681 →
Continuity (2)
Continuation 17552015 · Dec 15, 2021
Related Publication 20240319911A1 · Sep 26, 2024
References Cited (19)
US 11061735B2 · Li · 2021 [cited by applicant]
US 12019904B2 · Kommareddy et al. · 2024 [cited by applicant]
US 20170322893A1 · Tourrilhes et al. · 2017 [cited by applicant]
US 20210216227A1 · Kazi et al. · 2021 [cited by applicant]
US 20220317883A1 · Ramanan et al. · 2022 [cited by applicant]
US 20220413922A1 · Hamlin et al. · 2022 [cited by applicant]
US 20230185478A1 · Kommareddy et al. · 2023 [cited by applicant]
“Compute Express Link”, CXL Consortium [retrieved Oct. 14, 2021]. Retrieved from the Internet <https://www.computeexpresslink.org/>., Mar. 11, 2019, 2 Pages. [cited by applicant]
“Educational Materials”, Gen-Z Consortium [retrieved Oct. 14, 2021]. Retrieved from the Internet <https://genzconsortium.org/educational-materials/>., 2016, 6 Pages. [cited by applicant]
“HPE Unveils Computer Built for the Era of Big Data”, Hewlett Packard Enterprise Development LP [retrieved Oct. 14, 2021]. Retrieved from the Internet <https://www.hpe.com/us/en/newsroom/press-release/2017/05/a-new-comp… [cited by applicant]
U.S. Appl. No. 17/552,015 , “Final Office Action”, U.S. Appl. No. 17/552,015, Dec. 7, 2023, 10 pages. [cited by applicant]
U.S. Appl. No. 17/552,015 , “Non-Final Office Action”, U.S. Appl. No. 17/552,015, May 10, 2023, 9 pages. [cited by applicant]
U.S. Appl. No. 17/552,015 , “Notice of Allowance”, U.S. Appl. No. 17/552,015, Feb. 15, 2024, 8 pages. [cited by applicant]
Cheptsov, Alexey , et al., “HPC in Big Data Age: An Evaluation Report for Java-Based Data-Intensive Applications Implemented with Hadoop and OpenMPI”, EuroMPI/ASIA '14: Proceedings of the 21st European MPI Users' Group … [cited by applicant]
Keeton, Kimberly , et al., “Persistent memory: new tier or storage replacement?”, Hewlett Packard Enterprise [retrieved Oct. 14, 2021]. Retrieved from the Internet <https://www.snia.org/sites/default/files/SDC/2017/pres… [cited by applicant]
Kommareddy, Vamsee Reddy, et al., “Enforcing Fairness in Disaggregated Non-Volatile Memory Systems”, National Technology & Engineering Solutions of Sandia [retrieved Oct. 12, 2021]. Retrieved from the Internet <https://… [cited by applicant]
Kommareddy, Vamsee Reddy, et al., “Exploring Allocation Policies in Disaggregated Non-Volatile Memories”, MCHPC'18: Proceedings of the Workshop on Memory Centric High Performance Computing [retrieved Oct. 14, 2021]. Ret… [cited by applicant]
Kommareddy, Vamsee Reddy, et al., “Page Migration Support for Disaggregated Non-Volatile Memories”, MEMSYS '19: Proceedings of the International Symposium on Memory Systems [retrieved Oct. 12, 2021]. Retrieved from the … [cited by applicant]
Lim, Kevin , et al., “Disaggregated Memory for Expansion and Sharing in Blade Servers”, ACM SIGARCH Computer Architecture News, vol. 37, No. 3 [retrieved Oct. 13, 2021]. Retrieved from the Internet <https://web.eecs.umi… [cited by applicant]