SHARED TOP LEVEL DIGITAL-TO-ANALOG PARALLEL DATA BUS

1 . An integrated circuit comprising:

N analog circuit blocks, each comprising at most X data registers;

a bidirectional M-bit parallel data bus coupled to each of the N analog circuit blocks;

an external data port configured to receive data external to the integrated circuit; and

an interface circuit coupled to the external data port and the bidirectional M-bit parallel data bus, the interface circuit comprising

an analog circuit block selection output coupled to each of the N analog circuit blocks and configured to select an analog circuit block using at most N signals,

a register selection output coupled to each of the N analog circuit blocks and configured to select a data register using at most X signals, and

a mode selection output coupled to each of the N analog circuit blocks and configured to control the direction of data flow between the N analog circuit blocks and the interface circuit on the bidirectional M-bit parallel data bus.

2 . The integrated circuit of claim 1 , further comprising:

a non-volatile memory (NVM) coupled to the interface circuit and configured to read and write configuration data to and from selected data registers of selected analog circuit blocks over the bidirectional M-bit parallel data bus.

3 . The integrated circuit of claim 1 , wherein the register selection output is a log 2 X-bit register address coupled to each of the N analog circuit blocks.

4 . The integrated circuit of claim 1 , wherein the register selection output comprises X signals coupled to each of the N analog circuit blocks, each of the X signals being configured to select one of the at most X data registers of a respective analog circuit block.

5 . The integrated circuit of claim 1 , wherein the analog circuit block selection output is a log 2 N-bit block address coupled to each of the N analog circuit blocks.

6 . The integrated circuit of claim 1 , wherein the analog circuit block selection output comprises N signals each coupled to a corresponding analog circuit block, each of the N signals being configured to select one of the N analog circuit blocks.

7 . The integrated circuit of claim 1 , wherein the mode selection output consists of a single bit coupled to each of the N analog circuit blocks and configured to toggle the mode of the selected analog circuit block between write mode and read mode.

8 . The integrated circuit of claim 1 , wherein the mode selection output comprises a write enable signal and a read enable signal both coupled to each of the N analog circuit blocks, the write enable signal being configured to enable write mode of the selected analog circuit block and the read enable signal being configured to enable read mode of the selected analog circuit block.

9 . An integrated circuit comprising:

N analog circuit blocks, each comprising at most X data registers;

a bidirectional M-bit parallel data bus coupled to each of the N analog circuit blocks;

an external data port configured to receive data external to the integrated circuit;

an interface circuit coupled to the external data port and the bidirectional M-bit parallel data bus, the interface circuit comprising

an analog circuit block selection output coupled to each of the N analog circuit blocks and configured to select an analog circuit block using at most N signals,

a register selection output coupled to each of the N analog circuit blocks and configured to select a data register using log 2 X signals, the register selection output being a log 2 X-bit register address coupled to each of the N analog circuit blocks, and

a mode selection output coupled to each of the N analog circuit blocks and configured to control the direction of data flow between the N analog circuit blocks and the interface circuit on the bidirectional M-bit parallel data bus; and

a non-volatile memory (NVM) coupled to the interface circuit and configured to read and write configuration data to and from selected data registers of selected analog circuit blocks over the bidirectional M-bit parallel data bus.

10 . The integrated circuit of claim 9 , wherein X is 256, the register selection output being an 8-bit register address.

11 . The integrated circuit of claim 9 , wherein M is 8, the bidirectional M-bit parallel data bus being an 8-bit parallel data bus.

12 . The integrated circuit of claim 9 , wherein the analog circuit block selection output is a log 2 N-bit block address coupled to each of the N analog circuit blocks.

13 . The integrated circuit of claim 12 , wherein N is at most 16, the analog circuit block selection output being a 4-bit block address.

14 . The integrated circuit of claim 9 , wherein the analog circuit block selection output comprises N signals each coupled to a corresponding analog circuit block, each of the N signals being configured to select one of the N analog circuit blocks.

15 . The integrated circuit of claim 9 , wherein the mode selection output consists of a single bit coupled to each of the N analog circuit blocks and configured to toggle the mode of the selected analog circuit block between write mode and read mode.

16 . The integrated circuit of claim 9 , wherein the mode selection output comprises a write enable signal and a read enable signal both coupled to each of the N analog circuit blocks, the write enable signal being configured to enable write mode of the selected analog circuit block and the read enable signal being configured to enable read mode of the selected analog circuit block.

17 . A method of transferring configuration data between an interface circuit of an integrated circuit and a data register of an analog circuit block, the method comprising:

selecting a first analog circuit block from N analog circuit blocks of the integrated circuit by asserting at most N block selection signals at an analog circuit block selection output of the interface circuit coupled to each of the N analog circuit blocks;

selecting a first data register from at most X data registers of the first analog circuit block by asserting at most X block selection signals at a register selection output of the interface circuit coupled to each of the N analog circuit blocks;

enabling a data output of the interface circuit coupled to a bidirectional M-bit parallel data bus to transmit first configuration data over the bidirectional M-bit parallel data bus to the first analog circuit block, the bidirectional M-bit parallel data bus being coupled to each of the N analog circuit blocks; and

writing the first configuration data from the bidirectional M-bit parallel data bus to the first data register by asserting, after enabling the data output of the interface circuit, a write enable signal at a mode selection output of the interface circuit coupled to each of the N analog circuit blocks.

18 . The method of claim 17 , further comprising:

reading the first configuration data from nonvolatile memory of the integrated circuit to receive the first configuration data at the data output of the interface circuit; and

repeating the following steps for each additional data register of the first analog circuit block:

selecting an additional first data register from the at most X data registers of the first analog circuit block by asserting at most X block selection signals at the register selection output;

reading additional first configuration data from the nonvolatile memory;

transmitting the additional first configuration data over the bidirectional M-bit parallel data bus to the first analog circuit block; and

writing the additional first configuration data in the corresponding additional first data register; and

repeating the previous steps for each additional analog circuit block of the N analog circuit blocks.

19 . The method of claim 17 , further comprising:

selecting a second analog circuit block from the N analog circuit blocks by asserting at most N block selection signals at the analog circuit block selection output;

selecting a second data register from the at most X data registers of the second analog circuit block by asserting at most X block selection signals at the register selection output;

enabling a data output of the second analog circuit block coupled to the bidirectional M-bit parallel data bus to transmit second configuration data over the bidirectional M-bit parallel data bus to the interface circuit; and

reading the second configuration data from the bidirectional M-bit parallel data bus by asserting, after enabling the data output of the second analog circuit block, a read enable signal at the mode selection output.

20 . The method of claim 19 , further comprising:

writing the second configuration data in nonvolatile memory of the integrated circuit; and

repeating the following steps for each additional data register of the second analog circuit block:

selecting an additional second data register from the at most X data registers of the second analog circuit block by asserting at most X block selection signals at the register selection output;

transmitting additional second configuration data from the additional second data register over the bidirectional M-bit parallel data bus to the interface circuit; and

writing the additional second configuration data in the nonvolatile memory of the integrated circuit; and

repeating the previous steps for each additional analog circuit block of the N analog circuit blocks.