MEMORY CIRCUIT COMPRISING ELECTRONIC CELLS AND A CONTROL CIRCUIT
A memory circuit includes a memory array formed by electronic cells. Each electronic cell includes an integrated stack having, successively, a first electrode, an intermediate layer formed by an ovonic threshold switching layer, and a resistor connected to the intermediate layer. A control circuit is connected to the electronic cell. The control circuit is structured and configured to apply, between the first electrode and the resistor, a first voltage impulse of a first polarity to set a first logic state of the electronic cell and a second voltage impulse of a second polarity, opposite the first polarity, to set a second logic state of the electronic cell.
1 . A memory circuit, comprising:
a memory array comprising a plurality of electronic cells, wherein at least one electronic cell comprises an integrated stack having successively:
i) a first electrode;
ii) an intermediate layer comprising an ovonic threshold switching layer; and
iii) a resistor connected to the intermediate layer; and
a control circuit connected to the at least one electronic cell, wherein the control circuit is configured to apply, between the first electrode and the resistor, a first voltage impulse of a first polarity to set a first logic state of the electronic cell and apply a second voltage impulse of a second polarity, opposite the first polarity, to set a second logic state, different from the first logic state, of the electronic cell.
2 . The memory circuit according to claim 1 , wherein the ovonic threshold switching layer is made of a chalcogenide material.
3 . The memory circuit according to claim 1 , wherein only the intermediate layer is located between the first electrode and the resistor of the at least one electronic cell, and wherein the intermediate layer is solely the ovonic threshold switching layer.
4 . The memory circuit according to claim 3 , wherein the ovonic threshold switching layer has a thickness between 15 nm and 50 nm.
5 . The memory circuit according to claim 1 , wherein the control circuit comprises a plurality of bit lines and a plurality of word lines, wherein the at least one electronic cell is connected to a respective bit line by the resistor, and wherein the at least one electronic cell is connected to a respective word line by the first electrode.
6 . The memory circuit according to claim 1 , wherein the integrated stack further comprises a transistor connected to the resistor on an opposite side with respect to the intermediate layer.
7 . The memory circuit according to claim 6 , wherein the transistor is a MOSFET transistor.
8 . The memory circuit according to claim 6 , wherein the transistor is a FinFET transistor.
9 . The memory circuit according to claim 6 , wherein the ovonic threshold switching layer has a thickness between 5 nm and 10 nm.
10 . The memory circuit according to claim 6 , wherein the control circuit comprises a plurality of bit lines and a plurality of word lines, wherein the at least one electronic cell is connected to a respective word line by the transistor and wherein the at least one electronic cell is connected to a respective bit line by the first electrode.
11 . The memory circuit according to claim 10 , wherein the transistor comprises a drain and a gate and wherein the drain is connected to the resistor, and wherein the gate is connected to the respective word line.
12 . The memory circuit according to claim 10 , wherein the control circuit comprises, for each pair of bit line and word line, a respective inverter comprising a respective p-MOS transistor and a respective n-MOS transistor.
13 . A circuit, comprising:
an ovonic threshold switching memory cell formed by an integrated stack comprising a first electrode, a resistor, and an ovonic threshold switching layer having a first surface in contact with the first electrode and a second surface in contact with the resistor; and
a control circuit electrically connected to the ovonic threshold switching memory cell and configured to set a first logic state by applying, between the first electrode and the resistor, a first voltage impulse of a first polarity and to set a second logic state, different than the first logic state, by applying, between the first electrode and the resistor, a second voltage impulse of a second polarity opposite the first polarity.
14 . The circuit according to claim 13 , wherein the ovonic threshold switching layer is made of a chalcogenide material.
15 . The circuit according to claim 13 , wherein the ovonic threshold switching layer has a thickness between 15 nm and 50 nm.
16 . The circuit according to claim 13 , further comprising a transistor having a conduction terminal connected to the resistor and a control terminal connected to a word line.
17 . The circuit according to claim 16 , wherein the transistor is a MOSFET transistor, the conduction terminal is a drain and the control terminal is a gate.
18 . The circuit according to claim 16 , wherein the transistor is a FinFET transistor, the conduction terminal is a drain and the control terminal is a gate.