IP Library Granted Patent US 12,549,176
Granted Patent B2
US 12,549,176 · App. 18/738,840 · Granted Feb 10, 2026

Integratable voltage reference

Inventors: Andrea Gambero (Santo Stefano Ticino, IT); Sandro Rossi (Pavia, IT); Lorenzo Labate (Milan, IT); Simona Angela Cozzi (Legnano, IT); Giulio Ricotti (Broni, IT); Marco Marchesi (Corbetta, IT)
Assignee: STMicroelectronics International N.V.
H03K17/302G05F1/46H03K17/145H03K2217/0063H03K2217/0072
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Quick Facts
Patent No.
US 12,549,176
App. No.
18/738,840
Granted
Feb 10, 2026
Kind
B2
Abstract

An electronic system is disclosed. The system includes a Gallium Nitride (GaN) semiconductor die and further including, entirely disposed on the GaN semiconductor die i) a voltage reference circuit including GaN semiconductor transistors, the voltage reference circuit configured to generate a reference voltage, and ii) an electronic component including GaN semiconductor transistors and configured to generate a power output based on the reference voltage.

Claims (78)

1 . An electronic system, comprising a Gallium Nitride (GaN) semiconductor die and further comprising, entirely disposed on the GaN semiconductor die:

a voltage reference circuit comprising GaN semiconductor transistors, the voltage reference circuit configured to generate a reference voltage, and

an electronic component comprising GaN semiconductor transistors and configured to generate a power output based on the reference voltage,

wherein the voltage reference circuit comprises:

an amplifier comprising GaN semiconductor transistors, the amplifier comprising a first and a second input terminal and an output terminal;

a feedback stage comprising:

a first tract comprising a first GaN HEMT comprising a respective gate, source, and drain terminal, wherein the first GaN HEMT is connected to the first input terminal of the amplifier;

a second tract comprising:

a resistor connected, at a first end of the resistor, to the second input terminal of the amplifier; and

a second GaN HEMT comprising a respective gate, source and drain terminal, wherein the second HEMT is connected to a second end of the resistor,

wherein the second HEMT has an area which is Q times a respective area of the first HEMT, wherein Q is greater than 1,

wherein the first and second tracts are configured to respectively generate a first and second voltage at the first and second input terminal of the amplifier, respectively,

wherein the amplifier is configured to generate, at the output terminal, an amplifier voltage based on the first and second voltages,

wherein the feedback stage is configured to generate the reference voltage based on the amplifier voltage, and

wherein the reference voltage is a function of the area of the first and second HEMTs and a value of the resistor.

2 . The electronic system of claim 1 , wherein the reference voltage is a function of a ratio of the resistor and a second resistor and is a function of a ratio of the area of the first and second HEMTs.

3 . The electronic system of claim 1 , wherein the first and second HEMTs are depletion mode HEMTs.

4 . The electronic system of claim 1 , wherein the first and second HEMTs each comprise a metal gate structure contacting an AlGaN layer.

5 . The electronic system of claim 1 , wherein the reference voltage is a voltage at one of the first and second input terminals of the amplifier.

6 . The electronic system of claim 1 , further comprising:

a second resistor having a first end connected to the first input terminal of the amplifier and a second end connected to the second GaN HEMT; and

a third resistor having a first end connected to the first input terminal of the amplifier.

7 . The electronic system of claim 6 , wherein the reference voltage is a voltage at the second end of one of the first and second resistors.

8 . The electronic system of claim 6 , further comprising:

one or more third diodes connected between the first resistor and the second input terminal of the amplifier, wherein the first end of the second resistor is connected to the first input terminal of the amplifier by the one or more third diodes; and

one or more fourth diodes connected between the second resistor and the first input terminal of the amplifier, wherein the first end of the second resistor is connected to the first input terminal of the amplifier by the one or more fourth diodes,

wherein the reference voltage is a voltage at a second end of one of the first and second resistors.

9 . The electronic system of claim 1 , further comprising

a second resistor having a first end connected to the first and second GaN HEMTs and a second end connected to the first input terminal of the amplifier;

a third resistor having a first end connected to the first and second GaN HEMTs and a second end connected to the second input terminal of the amplifier; and

a fourth resistor having a first end connected to the first and second GaN HEMTs,

wherein the reference voltage is a voltage at a node to which the first and second GaN HEMTs are connected.

10 . A method of forming an electronic system, the method comprising:

providing a Gallium Nitride (GaN) semiconductor die;

forming a voltage reference circuit comprising GaN semiconductor transistors on the GaN semiconductor die, the voltage reference circuit configured to generate a reference voltage, and

forming an electronic component comprising GaN semiconductor transistors on the GaN semiconductor die, the electronic component configured to generate a power output based on the reference voltage,

wherein the voltage reference circuit comprises:

an amplifier comprising GaN semiconductor transistors, the amplifier comprising a first and a second input terminal and an output terminal;

a feedback stage comprising:

a first tract comprising a first GaN HEMT comprising a respective gate, source, and drain terminal, wherein the first GaN HEMT is connected to the first input terminal of the amplifier;

a second tract comprising:

a resistor connected, at a first end of the resistor, to the second input terminal of the amplifier; and

a second GaN HEMT comprising a respective gate, source and drain terminal, wherein the second HEMT is connected to a second end of the resistor,

wherein the second HEMT has an area which is Q times a respective area of the first HEMT, wherein Q is greater than 1,

wherein the first and second tracts are configured to respectively generate a first and second voltage at the first and second input terminal of the amplifier, respectively,

wherein the amplifier is configured to generate, at the output terminal, an amplifier voltage based on the first and second voltages,

wherein the feedback stage is configured to generate the reference voltage based on the amplifier voltage, and

wherein the reference voltage is a function of the area of the first and second HEMTs and a value of the resistor.

11 . The method of claim 10 , wherein the reference voltage is a function of a ratio of the resistor and a second resistor and is a function of a ratio of the area of the first and second HEMTs.

12 . The method of claim 10 , wherein the first and second HEMTs each comprise a metal gate structure contacting an AlGaN layer.

13 . The method of claim 10 , wherein the reference voltage is a voltage at one of the first and second input terminals of the amplifier.

14 . The method of claim 10 , further comprising:

forming a second resistor having a first end connected to the first input terminal of the amplifier and a second end connected to the second GaN HEMT; and

forming a third resistor having a first end connected to the first input terminal of the amplifier.

15 . The method of claim 14 , wherein the reference voltage is a voltage at the second end of one of the first and second resistors.

16 . The method of claim 14 , further comprising:

forming one or more third diodes connected between the first resistor and the second input terminal of the amplifier, wherein the first end of the second resistor is connected to the first input terminal of the amplifier by the one or more third diodes; and

forming one or more fourth diodes connected between the second resistor and the first input terminal of the amplifier, wherein the first end of the second resistor is connected to the first input terminal of the amplifier by the one or more fourth diodes,

wherein the reference voltage is a voltage at a second end of one of the first and second resistors.

17 . The method of claim 10 , further comprising:

forming a second resistor having a first end connected to the first and second GaN HEMTs and a second end connected to the first input terminal of the amplifier;

forming a third resistor having a first end connected to the first and second GaN HEMTs and a second end connected to the second input terminal of the amplifier; and

forming a fourth resistor having a first end connected to the first and second GaN HEMTs,

wherein the reference voltage is a voltage at a node to which the first and second GaN HEMTs are connected.

18 . An electronic system, comprising a Gallium Nitride (GaN) semiconductor die and further comprising, entirely disposed on the GaN semiconductor die a voltage reference circuit comprising GaN semiconductor transistors, the voltage reference circuit configured to generate a reference voltage, and the voltage reference circuit comprising:

an amplifier comprising GaN semiconductor transistors, the amplifier comprising a first and a second input terminal and an output terminal;

a feedback stage comprising:

a first tract comprising a first GaN HEMT comprising a respective gate, source, and drain terminal, wherein the first GaN HEMT is connected to the first input terminal of the amplifier;

a second tract comprising:

a resistor connected, at a first end of the resistor, to the second input terminal of the amplifier; and

a second GaN HEMT comprising a respective gate, source and drain terminal, wherein the second HEMT is connected to a second end of the resistor,

wherein the second HEMT has an area which is Q times a respective area of the first HEMT, wherein Q is greater than 1,

wherein the first and second tracts are configured to respectively generate a first and second voltage at the first and second input terminal of the amplifier, respectively,

wherein the amplifier is configured to generate, at the output terminal, an amplifier voltage based on the first and second voltages,

wherein the feedback stage is configured to generate the reference voltage based on the amplifier voltage, and

wherein the reference voltage is a function of the area of the first and second HEMTs and a value of the resistor.

19 . The electronic system of claim 18 , wherein the reference voltage is a function of a ratio of the resistor and a second resistor and is a function of a ratio of the area of the first and second HEMTs.

20 . The electronic system of claim 18 , wherein the first and second HEMTs each comprise a metal gate structure contacting an AlGaN layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2024
From: STMICROELECTRONICS S.R.L.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 069180/0793 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2024
From: GAMBERO, ANDREA; ROSSI, SANDRO; LABATE, LORENZO; COZZI, SIMONA ANGELA; RICOTTI, GIULIO; MARCHESI, MARCO
To: STMICROELECTRONICS S.R.L.
Reel/Frame 067701/0317 →
Continuity (1)
Related Publication 20250379574A1 · Dec 11, 2025
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