Using metadata to selectively perform data prestaging
View Patent ↗A computer-implemented method, according to one approach, includes: receiving a read request for data in memory and analyzing metadata from volumes that contain the requested data. The metadata maps sequential logical addresses of the requested data to their corresponding physical addresses. The computer-implemented method also includes determining whether the corresponding physical addresses storing the requested data are sequential. In response to determining that at least a predetermined number of the corresponding physical addresses are sequential, the requested data is prestaged from the sequential ones of the physical addresses. However, in response to determining that fewer than the predetermined number of the corresponding physical addresses are sequential, the computer-implemented method includes intentionally refraining from prestaging any of the requested data from the physical addresses.
1 . A computer-implemented method (CIM), comprising:
receiving a read request for data in memory;
analyzing metadata from volumes that contain the requested data, wherein the metadata maps sequential logical addresses of the requested data to their corresponding physical addresses;
determining whether the corresponding physical addresses storing the requested data are sequential;
in response to determining that at least a predetermined number of the corresponding physical addresses are sequential, prestaging the requested data from the sequential ones of the physical addresses; and
in response to determining that fewer than the predetermined number of the corresponding physical addresses are sequential, intentionally refraining from prestaging any of the requested data from the physical addresses.
2 . The CIM of claim 1 , wherein the volumes that contain the requested data are thin provisioned storage volumes, wherein the volumes have log structured array based architectures.
3 . The CIM of claim 1 , wherein the prestaging of the requested data from the sequential ones of the physical addresses includes:
causing portions of the requested data to be read from the sequential ones of the physical addresses before the corresponding ones of the sequential logical addresses are evaluated; and
storing the read portions of the requested data in cache.
4 . The CIM of claim 3 , further comprising, for each of the sequential logical addresses:
in response to determining that a given one of the sequential logical addresses maps to a respective one of the sequential physical addresses, accessing the prestaged portion of the requested data from the cache.
5 . The CIM of claim 3 , further comprising, for each of the sequential logical addresses:
in response to determining that a given one of the sequential logical addresses does not map to a respective one of the sequential physical addresses, causing a respective portion of the requested data to be read from a respective one of the physical addresses that corresponds to the given one of the sequential logical addresses.
6 . The CIM of claim 1 , wherein the memory includes magnetic disks, wherein the portions of the requested data read from the sequential ones of the physical addresses are stored in the cache prior to inspecting a first of the sequential logical addresses.
7 . The CIM of claim 1 , further comprising:
in response to the portions of the requested data read from the sequential ones of the physical addresses being stored in the cache, initiating the read request by evaluating a first of the sequential logical addresses,
wherein the read request is received by a caching layer.
8 . A computer program product (CPP), comprising:
a set of one or more computer-readable storage media; and
program instructions, collectively stored in the set of one or more storage media, for causing a processor set to perform the following computer operations:
receive a read request for data in memory;
analyze metadata from that contain the requested data, wherein the metadata maps sequential logical addresses of the requested data to their corresponding physical addresses, wherein the volumes have log structured array based architectures;
determine whether the corresponding physical addresses storing the requested data are sequential;
in response to determining that at least a predetermined number of the corresponding physical addresses are sequential, prestage the requested data from the sequential ones of the physical addresses; and
in response to determining that fewer than the predetermined number of the corresponding physical addresses are sequential, intentionally refrain from prestaging any of the requested data from the physical addresses.
9 . The CPP of claim 8 , wherein the volumes that contain the requested data are thin provisioned storage volumes.
10 . The CPP of claim 8 , wherein the prestaging of the requested data from the sequential ones of the physical addresses includes:
causing portions of the requested data to be read from the sequential ones of the physical addresses before the corresponding ones of the sequential logical addresses are evaluated; and
storing the read portions of the requested data in cache.
11 . The CPP of claim 10 , wherein the program instructions are for causing the processor set to further perform the following computer operations, for each of the sequential logical addresses:
in response to determining that a given one of the sequential logical addresses maps to a respective one of the sequential physical addresses, access the prestaged portion of the requested data from the cache.
12 . The CPP of claim 10 , wherein the program instructions are for causing the processor set to further perform the following computer operations, for each of the sequential logical addresses:
in response to determining that a given one of the sequential logical addresses does not map to a respective one of the sequential physical addresses, cause a respective portion of the requested data to be read from a respective one of the physical addresses that corresponds to the given one of the sequential logical addresses.
13 . The CPP of claim 8 , wherein the memory includes magnetic disks.
14 . The CPP of claim 8 , wherein the read request is received by a caching layer.
15 . A computer system (CS), comprising:
a processor set;
a set of one or more computer-readable storage media;
program instructions, collectively stored in the set of one or more storage media, for causing the processor set to perform the following computer operations:
receive a read request for data in memory;
analyze metadata from volumes that contain the requested data, wherein the metadata maps sequential logical addresses of the requested data to their corresponding physical addresses, wherein the volumes have log structured array based architectures;
determine whether the corresponding physical addresses storing the requested data are sequential;
in response to determining that at least a predetermined number of the corresponding physical addresses are sequential, prestage the requested data from the sequential ones of the physical addresses; and
in response to determining that fewer than the predetermined number of the corresponding physical addresses are sequential, intentionally refrain from prestaging any of the requested data from the physical addresses.
16 . The CS of claim 15 , wherein the volumes that contain the requested data are thin provisioned storage volumes.
17 . The CS of claim 15 , wherein the prestaging of the requested data from the sequential ones of the physical addresses includes:
causing portions of the requested data to be read from the sequential ones of the physical addresses before the corresponding ones of the sequential logical addresses are evaluated; and
storing the read portions of the requested data in cache.
18 . The CS of claim 17 , wherein the program instructions are for causing the processor set to further perform the following computer operations, for each of the sequential logical addresses:
in response to determining that a given one of the sequential logical addresses maps to a respective one of the sequential physical addresses, access the prestaged portion of the requested data from the cache.
19 . The CS of claim 17 , wherein the program instructions are for causing the processor set to further perform the following computer operations, for each of the sequential logical addresses:
in response to determining that a given one of the sequential logical addresses does not map to a respective one of the sequential physical addresses, cause a respective portion of the requested data to be read from a respective one of the physical addresses that corresponds to the given one of the sequential logical addresses.
20 . The CS of claim 15 , wherein the program instructions are for causing the processor set to further perform the following computer operations:
in response to the portions of the requested data read from the sequential ones of the physical addresses being stored in the cache, initiate the read request by evaluating a first of the sequential logical addresses;
in response to determining that the first of the sequential logical addresses maps to a respective one of the sequential physical addresses, access the prestaged portion of the requested data from the cache; and
in response to determining that the first of the sequential logical addresses does not map to a respective one of the sequential physical addresses, cause a respective portion of the requested data to be read from one of the physical addresses that corresponds to the first of the sequential logical addresses,
wherein the memory includes magnetic disks, wherein the read request is received by a caching layer.