Receiver device for two-wire bus

1 . A device comprising:

first and second terminals configured to be respectively connected to first and second conductors of a differential two-wire bus;

first and second identical resistive dividing bridges connected between a reference node and respectively first and second nodes, wherein the first and second nodes are respectively coupled with the first and second terminals;

third and fourth identical resistive dividing bridges connected between a supply node and respectively the first and second nodes; and

a reading circuit comprising:

first and second NMOS (n-channel metal oxide semiconductor) transistors having gates connected to each other and sources connected to an intermediary node of the second bridge;

third and fourth NMOS transistors having gates connected to each other and sources connected to a corresponding intermediary node of the first bridge;

fifth and sixth PMOS (p-channel metal oxide semiconductor) transistors having gates connected to each other and sources connected to an intermediary node of the fourth bridge;

seventh and eighth transistors having gates connected to each other and sources connected to a corresponding intermediary node of the third bridge;

wherein the second and third transistors have drains connected to a first current source;

wherein the sixth and seventh transistors have drains connected to a second current source; and

wherein the reading circuit is configured to determine a binary state of the bus from currents flowing through the first, fourth, fifth, and eighth transistors.

2 . The device of claim 1 , wherein:

the reference node is configured to receive a reference potential; and

the supply node is configured to receive a supply potential.

3 . The device of claim 2 , wherein the supply potential is preferably positive with respect to the reference potential.

4 . The device of claim 1 , wherein:

each of the first and second bridges comprises:

a first resistive element connected between the reference node and the intermediary node of the bridge; and

a second resistive element connected between the intermediary node of the bridge and, respectively, the first node and the second node; and

each of the third and fourth bridges comprises:

a third resistive element connected between the supply node and the intermediary node of the bridge; and

a fourth resistive element connected between the intermediary node of the bridge and, respectively, the first node and the second node.

5 . The device of claim 4 , wherein a ratio of resistance value of the first resistive element to the resistance value of the second resistive element is equal to a ratio of resistance value of the third resistive element to the resistance value of the fourth resistive element.

6 . The device of claim 4 , wherein:

in each of the first and second bridges, the first and second resistive elements are configured so that:

an AC voltage on the intermediary node of the first bridge corresponds to an AC voltage on the first terminal divided by a factor A, and

an AC voltage on the intermediary node of the second bridge corresponds to an AC voltage on the second terminal divided by the factor A;

in each of the third and fourth bridges, the third and fourth resistive elements are configured so that:

an AC voltage on the intermediary node of the third bridge corresponds to an AC voltage on the first terminal divided by the factor A, and

an AC voltage on the intermediary node of the fourth bridge corresponds to an AC voltage on the second terminal divided by the factor A.

7 . The device of claim 4 , wherein:

in each of the first and second bridges, a resistance value of the first resistive element is lower than a resistance value of the second resistive element; and

in each of the third and fourth bridges, a resistance value of the third resistive element is lower than a resistance value of the fourth resistive element.

8 . The device of claim 1 , wherein:

a fifth resistive element couples the first node with the first terminal; and

a sixth resistive element identical to the fifth resistive element couples the second node with the second terminal.

9 . The device of claim 1 , wherein the reading circuit comprises:

a first biasing circuit configured to:

apply a first biasing potential to the gates of the first and second transistors, and

apply a second biasing potential to the gates of the third and fourth transistors, wherein the second potential is different from the first potential; and

a second biasing circuit configured to:

apply a third biasing potential to the gates of the fifth and sixth transistors, and

apply a fourth biasing potential to the gates of the seventh and eighth transistors, wherein the fourth potential is different from the third potential.

10 . The device of claim 9 , wherein:

the first biasing circuit comprises:

the first current source,

a seventh resistive element connected between the drain and the gate of the second transistor,

an eighth resistive element having a same resistance value as the seventh resistive element, connected between the drain and the gate of the third transistor, and

a third current source connected to the gates of the third and fourth transistors; and

the second biasing circuit comprises:

the second current source,

a ninth resistive element connected between the drain and the gate of the sixth transistor,

a tenth resistive element having a same resistance value as the ninth resistive element, connected between the drain and the gate of the seventh transistor, and

a fourth current source connected to the gates of the seventh and eighth transistors.

11 . The device of claim 1 , wherein the reading circuit comprises:

a first circuit for copying current configured to draw, at a node for summing a current of the reading circuit, an image of a current through the first transistor;

a second circuit for copying current configured to deliver, at the node for summing the current, an image of a current through the fourth transistor;

a third circuit for copying current configured to deliver, at the node for summing the current, an image of a current through the fifth transistor; and

a fourth circuit for copying current configured to draw, at the node for summing the current, an image of a current through the eighth transistor.

12 . The device of claim 11 , wherein:

the first circuit for copying current comprises:

a first current mirror with PMOS transistors, and

a second current mirror with NMOS transistors,

wherein the first current mirror couples the drain of the first transistor with the second current mirror, and the second current mirror couples the first mirror with the node for summing;

the second circuit for copying current comprises a third current mirror with PMOS transistors coupling the drain of the fourth transistor with the node for summing;

the third circuit for copying current comprises:

a fourth current mirror with NMOS transistors, and

a fifth current mirror with PMOS transistors,

wherein the fourth current mirror couples the drain of the fifth transistor with the fifth current mirror, and the fifth current mirror couples the fourth current mirror with the node for summing; and

the fourth circuit for copying current comprises sixth current mirror with NMOS transistors, coupling the drain of the eighth transistor with the node for summing.

13 . The device of claim 1 , wherein the reading circuit comprises a transimpedance amplifier configured to:

receive a current determined by the currents flowing through the first, fourth, fifth and eighth transistors, and

deliver, from the received current, a binary voltage representative of a differential voltage of the bus.

14 . The device of claim 12 , wherein the reading circuit comprises a transimpedance amplifier having an input coupled with the node for summing and an output configured to deliver, from a current received at its input, a binary voltage representative of a differential voltage of the bus.

15 . The device of claim 13 , wherein the transimpedance amplifier comprises:

an inverter, and

a resistive element connected between an input of the inverter and an output of the inverter.

16 . A reading circuit for a differential two-wire bus device, the reading circuit comprising:

a first differential pair of NMOS (n-channel metal oxide semiconductor) transistors having sources connected to a first intermediary node of a first resistive dividing bridge;

a second differential pair of NMOS transistors having sources connected to a second intermediary node of a second resistive dividing bridge;

a third differential pair of PMOS (p-channel metal oxide semiconductor) transistors having sources connected to a third intermediary node of a third resistive dividing bridge;

a fourth differential pair of PMOS transistors having sources connected to a fourth intermediary node of a fourth resistive dividing bridge;

a first current source connected to drains of one transistor from the first differential pair and one transistor from the second differential pair;

a second current source connected to drains of one transistor from the third differential pair and one transistor from the fourth differential pair;

a first biasing circuit configured to apply different biasing potentials to gates of the first and second differential pairs;

a second biasing circuit configured to apply different biasing potentials to gates of the third and fourth differential pairs; and

a current summing node, wherein the reading circuit is configured to determine a binary state of the bus based on currents flowing through one transistor from each of the four differential pairs to the current summing node.

17 . The reading circuit of claim 16 , further comprising:

a first current copying circuit configured to draw, at the current summing node, an image of a current through a first transistor of the first differential pair;

a second current copying circuit configured to deliver, at the current summing node, an image of a current through a second transistor of the second differential pair;

a third current copying circuit configured to deliver, at the current summing node, an image of a current through a first transistor of the third differential pair; and

a fourth current copying circuit configured to draw, at the current summing node, an image of a current through a second transistor of the fourth differential pair.

18 . The reading circuit of claim 17 , further comprising a transimpedance amplifier having an input coupled to the current summing node and an output configured to deliver a binary voltage representative of a differential voltage of the bus, wherein the transimpedance amplifier comprises an inverter and a resistive element connected between an input of the inverter and an output of the inverter.

19 . A device for reading from a differential two-wire bus, comprising:

a first terminal and a second terminal configured to be respectively connected to first and second conductors of the differential two-wire bus;

a first resistive dividing bridge connected between a reference node and a first node, wherein the first node is coupled to the first terminal;

a second resistive dividing bridge connected between the reference node and a second node, wherein the second node is coupled to the second terminal;

a third resistive dividing bridge connected between a supply node and the first node;

a fourth resistive dividing bridge connected between the supply node and the second node; and

a reading circuit comprising:

a first differential pair of NMOS (n-channel metal oxide semiconductor) transistors having sources connected to an intermediary node of the second resistive dividing bridge;

a second differential pair of NMOS transistors having sources connected to an intermediary node of the first resistive dividing bridge;

a third differential pair of PMOS (p-channel metal oxide semiconductor) transistors having sources connected to an intermediary node of the fourth resistive dividing bridge;

a fourth differential pair of PMOS transistors having sources connected to an intermediary node of the third resistive dividing bridge;

a first biasing circuit configured to apply different biasing potentials to gates of the first and second differential pairs; and

a second biasing circuit configured to apply different biasing potentials to gates of the third and fourth differential pairs;

wherein the reading circuit is configured to determine a binary state of the bus based on currents flowing through the first, second, third, and fourth differential pairs.

20 . The device of claim 19 , wherein the first biasing circuit is configured to apply a first biasing potential to the gates of the first and second differential pairs that is higher than a second biasing potential applied to the gates of the third and fourth differential pairs, such that when a common-mode voltage of the bus decreases below a nominal value, the first and second differential pairs remain operational while the third and fourth differential pairs become non-operational, and when the common-mode voltage increases above the nominal value, the third and fourth differential pairs remain operational while the first and second differential pairs become non-operational.