Memory device and a method of operating the same device
A memory device and a method of operating the memory device are provided. The memory device includes a memory cell array including a plurality of memory cells to store data, an error correction code (ECC) circuit, and an error check and scrub (ECS) circuit. The ECC circuit reads the data from the memory cell array and corrects errors in the data. The ECS circuit performs a scrubbing operation on the memory cell array and transmits a signal for an error address detected based on the scrubbing operation to an external circuit and stores the error address which was transmitted.
1 . A memory device, comprising:
a memory cell array including a plurality of memory cells configured to store data;
an error correction code (ECC) circuit configured to read the data from the memory cell array and correct errors in the data; and
an error check and scrub (ECS) circuit configured to:
perform a scrubbing operation on the memory cell array in an ECS mode,
transmit a signal for an error address detected based on the scrubbing operation to a memory controller, and
store the error address transmitted to the memory controller,
wherein the ECS circuit comprises:
a first register in which a first row address for the error address is logged; and
a second register in which the error address transmitted to the memory controller is stored, wherein the second register includes an error row address table in which the error address transmitted to the memory controller is stored,
wherein the ECS circuit is further configured to:
compare the first row address with the error row address table; and
log the first row address according to a result of comparing the first row address.
2 . The memory device of claim 1 , wherein:
the ECS circuit is further configured to remove the first row address from the first register after the error address is transmitted to the memory controller.
3 . The memory device of claim 2 , wherein:
the ECS circuit is further configured to log a second row address in the first register after the error address is transmitted to the memory controller.
4 . The memory device of claim 3 , wherein:
the second row address and the error address stored in the second register are different from each other.
5 . The memory device of claim 1 , wherein:
the first register is configured to store together a first count value, which is a number of subpages including a correctable error (CE) in the first row address, and the first row address.
6 . The memory device of claim 5 , wherein:
the ECS circuit is configured to perform a scrubbing operation on a second row address, which is different from the first row address, before transmission of the error address to the memory controller,
the first count value is greater than a second count value, which is a number of subpages including CE in the second row address.
7 . The memory device of claim 1 , wherein:
the first row address comprises a UE subpage including an uncorrectable error (UE).
8 . The memory device of claim 7 , wherein:
the ECC circuit is configured to detect the UE subpage through a single error correction and double error detection (SEC-DED) code.
9 . The memory device of claim 1 , wherein:
the ECS circuit is configured to transmit the first row address, which is logged in the first register, as the error address in response to a report command received from the memory controller.
10 . The memory device of claim 9 , wherein:
the report command is a mode register read (MRR) command.
11 . A method of operating a memory device comprising an error check and scrub (ECS) circuit, comprising:
receiving a first report command;
transmitting, by the ECS circuit, a candidate row address logged in a first register of the ECS circuit to a memory controller in response to receiving the first report command;
storing, by the ECS circuit, the transmitted candidate row address in an error row address table that is stored within a second register of the ECS circuit;
performing, by the ECS circuit, a scrubbing operation in an ECS mode on a first row address among row addresses of a memory cell array;
comparing, by the ECS circuit, the first row address with the error row address table; and
logging, by the ECS circuit, the first row address according to a result of comparing the first row address.
12 . The method of operating the memory device of claim 11 , further comprising:
generating the error row address table; and
removing the row address from the first register.
13 . The method of operating the memory device of claim 11 , wherein:
the first row address is logged to the first register based on an error address in the error row address table being different from the first row address.
14 . The method of operating the memory device of claim 13 , wherein:
the first row address includes a subpage including a UE.
15 . The method of operating the memory device of claim 13 , further comprising:
performing a scrubbing operation in the ECS mode on a second row address which is different from the first row address;
comparing the second row address with the error row address table; and
based on the second row address being different from the error address in the error row address table and based on a first count value being smaller than a second count value, logging the second row address to the first register, wherein the first count value is a number of subpages including CE in the first row address, and wherein the second count value is a number of subpages including CE in the second row address.
16 . The method of operating the memory device of claim 11 , further comprising:
receiving a second report command after the first report command;
transmitting the logged first row address to a memory controller in response to the second report command; and
storing the transmitted first row address in the error row address table.
17 . A memory device, comprising:
a memory cell array including a plurality of memory cells disposed at intersections of a plurality of word lines and a plurality of bit lines;
an ECC circuit configured to read data from the memory cell array and configured to correct errors in the data; and
an ECS circuit configured to:
perform a scrubbing operation on the memory cell array in an ECS mode,
transmit a signal for an error address detected based on the scrubbing operation to a memory controller,
store the error address transmitted to the memory controller inside the ECS circuit; and
a row decoder including a repair unit configured to perform a repair operation on the plurality of word lines based on the error address transmitted to the memory controller,
wherein the ECS circuit comprises:
a first register in which a first row address for the error address is logged; and
a second register in which the error address transmitted to the memory controller is stored, wherein the second register includes an error row address table in which the error address transmitted to the memory controller is stored,
wherein the ECS circuit is further configured to:
compare the first row address with the error row address table; and
log the first row address according to a result of comparing the first row address.