Selectively erasing one of multiple erase blocks coupled to a same string by creating a pseudo PN junction
Erase operations can be performed selectively on one of erase blocks or a memory array coupled to the same string by creating a pseudo PN junction that is located adjacent to the selected erase block. The pseudo PN junction is created by including channel inversion at least on those portions of the string coupled to unselected erase blocks, which further creates a flow of electrons. As a result of the channel inversion (along with channel accumulation created adjacent to the channel inversion), the flow of gate induced drain leakage (GIDL) holes are further generated from the pseudo PN junction and GIDL holes are induced to tunnel into memory cells of the selected erase block.
1 . An apparatus, comprising:
a memory array comprising a plurality of strings of memory cells, wherein a first string of the plurality of strings is coupled to one or more first select transistors on a first end coupled to a sense line and one or more second select transistors on a second end coupled to a source line, the first string further comprises:
a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and
a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block, wherein the first group of access lines and the second group of access lines are separated by a separation region; and
a controller coupled to the memory array and configured to, in order to selectively erase the second erase block independently of the first erase block:
apply a voltage having a first value to the sense line;
apply a voltage having a second value greater than the first value to the first group of access lines to induce a channel inversion on a portion of the first string corresponding to the first group of access lines to create a pseudo PN junction at the separation region; and
apply a voltage having a third value less than the first value to the second group of access lines to erase data stored on the second erase block using gate induced drain leakage (GIDL) holes generated at the separation region.
2 . The apparatus of claim 1 , wherein the first string further comprises a third group of memory cells coupled to a third group of access lines and corresponding to a third erase block.
3 . The apparatus of claim 2 , wherein:
the third group of access lines are located between the second group of access lines and the source line
the controller is configured to, in order to selectively erase the second erase block independently of the first erase block, apply a voltage having a fourth value equal to or less than the first value to the third group of access lines to block GIDL holes from being carried through a portion of the first string corresponding to the third group of access lines and retain data stored on the third erase block.
4 . The apparatus of claim 2 , wherein:
the third group of access lines are located between the sense line and the first group of access lines, while the first group of access lines are located between the third group of access lines and the separation region; and
wherein the controller is configured to, in order to selectively erase the second erase block independently of the first erase block, apply a voltage having the second value to the third group of access lines to induce a channel inversion on a portion of the first string corresponding to the third group of access lines to create a pseudo PN junction at the separation region.
5 . An apparatus, comprising:
a memory array comprising a plurality of strings of memory cells, wherein a first string of the plurality of strings is coupled to one or more first select transistors on a first end coupled to a sense line and one or more second select transistors on a second end coupled to a source line, the first string further comprises:
a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block;
a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block; and
a first number of dummy memory cells coupled to a respective number of first dummy access lines located between the second group of access lines and the source line; and
a controller coupled to the memory array and configured to, in order to selectively erase the second erase block independently of the first erase block:
apply a voltage having a first value to the source line;
apply a voltage having a second value greater than the first value to one or more select gate source lines coupled to the one or more second select transistors to induce a channel inversion on the one or more second select transistors coupled to the one or more select gate source lines and create a pseudo PN junction on a portion of the first string corresponding to the number of first dummy access lines; and
apply a voltage having a third value less than the first value to the second group of access lines to erase data stored on the second erase block using gate induced drain leakage (GIDL) holes generated at a portion of the first string corresponding to the number of first dummy access lines.
6 . The apparatus of claim 5 , wherein the controller is configured to:
apply a voltage having the second value to one or more access lines of the number of first dummy access lines that are adjacent to the one or more second select transistors to further induce a channel inversion on the one or more access lines of the number of first dummy access lines that are adjacent to the one or more second select transistors and create a pseudo PN junction on a portion of the first string corresponding to the one or more number of first dummy access lines that are adjacent to the second erase block.
7 . The apparatus of claim 5 , wherein the controller is configured to:
apply a voltage having the third value to one or more access lines of the number of first dummy access lines that are adjacent to the second erase block to induce channel accumulation on a portion of the first string coupled to the one or more access lines of the number of first dummy access lines that are adjacent to the second erase block and create a pseudo PN junction on a portion of the first string corresponding to the one or more number of first dummy access lines that are adjacent to the one or more second select transistors.
8 . The apparatus of claim 5 , wherein the controller is further configured to, in order to selectively erase the second erase block independently of the first erase block:
apply a voltage having a fourth value equal to or less than the first value to the first group of access lines to block GIDL holes from being carried through a portion of the first string corresponding to the first group of access lines and retain data stored on the second erase block.
9 . The apparatus of claim 5 , wherein the controller is configured to apply a voltage having the second value to the one or more select gate source lines to selectively erase the second erase block independently of the first erase block.
10 . The apparatus of claim 5 , wherein the memory array further comprises:
a third erase block comprising a third group of memory cells coupled to a third group of access lines and the first string; and
a number of second dummy access lines located between the second group of access line and the third group of access lines, wherein the third group of access lines are located between the number of second dummy access lines and a source line.
11 . The apparatus of claim 10 , wherein the controller is configured to, in order to selectively erase the second erase block independently of the first and third erase blocks:
apply a voltage having the first value to the source line;
apply a voltage having the second value to the one or more select gate source lines and the third group of access lines to induce a channel inversion on a portion of the first string corresponding to the third group of access lines and create a pseudo PN junction on a portion of the first string corresponding to the number of second dummy access lines; and
apply a voltage having the third value to the second group of access lines to erase data stored on the second erase block using GIDL holes generated at a portion of the first string corresponding to the number of second dummy access lines.
12 . The apparatus of claim 10 , wherein:
the memory array further comprises a number of third dummy access lines located between the first group of access lines and the second group of access lines; and
the controller is configured to, in order to selectively erase the first erase block independently of the second and third erase blocks:
apply a voltage having the first value to the source line;
apply a voltage having the second value to the one or more select gate source lines, the second group of access lines, the number of first dummy access lines, the number of second dummy access lines, and the third group of access lines to induce a channel inversion on a corresponding portion of the first string corresponding to the second group of access lines, the number of first dummy access lines, the number of second dummy access lines, and the third group of access lines and create a pseudo PN junction on a portion of the first string corresponding to the number of third dummy access lines; and
apply a voltage having the third value to the first group of access lines to erase data stored on the first erase block using GIDL holes generated at a portion of the first string corresponding to the number of third dummy access lines.
13 . A method for performing an erase operation on a memory array comprising a first erase block and a second erase block that are coupled to one or more first strings, the method further comprising:
in order to selectively erase the second erase block independently of the first erase block:
applying a voltage having a first value to a sense line, wherein:
the first erase block comprises a first group of memory cells coupled to a first group of access lines and the one or more first strings; and
the second erase block comprises a second group of memory cells coupled to a second group of access lines and the one or more first strings;
applying a voltage having a second value greater than the first value to the first group of access lines or to one or more select gate source lines to induce channel inversion on a portion of the one or more first strings corresponding to the first group of access lines or the one or more select gate source lines and generate gate induced drain leakage (GIDL) holes at a number of first dummy access lines located adjacent to the second group of access lines; and
applying a voltage having a third value less than the first value to the second group of memory cells to remove electrical charge stored on the second erase block using the GIDL holes.
14 . The method of claim 13 , wherein:
the first group of access lines and the second group of access lines are separated by the number of first dummy access lines; and
the method further comprises:
applying a voltage having the second value to the first group of access lines to induce channel inversion on the portion of the one or more first strings corresponding to the first group of access lines;
applying a voltage having the second value to one or more select gate drain lines to induce channel inversion on respective select transistors coupled to the one or more select gate drain lines.
15 . The method of claim 14 , further comprising:
applying a voltage having the second value to one or more access lines of the number of first dummy access lines that are adjacent to the first group of access lines to further induce channel inversion on a portion of the one or more first strings corresponding to the one or more access lines of the number of first dummy access lines.
16 . The method of claim 14 , further comprising:
applying a voltage having the third value to one or more access lines of the number of first dummy access lines that are adjacent to the second group of access lines to generate GIDL holes at one or more access lines of the number of first dummy access line that are adjacent to the first group of access lines.
17 . The method of claim 13 , wherein:
the second group of access lines and the one or more select gate source lines are separated by the number of first dummy access lines; and
the method further comprises:
applying a voltage having the second value to the one or more select gate source lines to induce channel inversion on the portions of the one or more first strings corresponding to the one or more select gate source lines; and
applying a voltage having a fourth value equal to or less than the first value to the first group of access lines to block the GIDL holes from being carried through a portion of the one or more first strings corresponding to the first group of access lines.
18 . The method of claim 13 , wherein the memory array further comprises:
a third erase block comprising a third group of memory cells coupled to a third group of access lines and the one or more first strings; and
one or more second dummy access lines located between the second group of access line and the third group of access lines, wherein the third group of access lines are located between the one or more second dummy access lines and a source line.
19 . The method of claim 18 , further comprising applying a voltage having a fourth value equal to or less than the first value to the third group of access lines to block the GIDL holes from being carried through a portion of the one or more first strings corresponding to the third group of access lines.
20 . The method of claim 18 , further comprising performing an erase operation selectively on the third erase block and independently of the first and second erase blocks by:
applying a voltage having the first value to the sense line;
applying a voltage having the second value greater to the first and second groups of access lines to induce channel inversion on a portion of the one or more first strings corresponding to the first and second groups of access lines and generate GIDL holes at the one or more second number of dummy access lines located adjacent to the second group of access lines; and
applying a voltage having the third value to the third group of memory cells to remove electrical charge stored on the third erase block using the GIDL holes.