Solar cell emitter region fabrication with differentiated p-type and n-type architectures and incorporating a multi-purpose passivation and contact layer

1 . A method of fabricating alternating N-type and P-type emitter regions of a solar cell, the method comprising:

forming an N-type silicon layer on a first thin dielectric layer formed on a back surface of a substrate;

forming an insulating layer on the N-type silicon layer;

patterning the insulating layer and the N-type silicon layer to form N-type silicon regions having an insulating cap thereon;

forming a second thin dielectric layer on exposed sides of the N-type silicon regions;

forming a P-type silicon layer on a third thin dielectric layer formed on the back surface of the substrate, and on the second thin dielectric layer and the insulating cap of the N-type silicon regions;

forming a P-type amorphous silicon layer on the P-type silicon layer;

patterning the P-type amorphous silicon layer and the P-type silicon layer to form isolated P-type emitter regions and to form contact openings in regions of the P-type amorphous silicon layer and the P-type silicon layer above the insulating cap of the N-type silicon regions;

patterning the insulating cap through the contact openings to expose portions of the N-type silicon regions; and

forming conductive contacts to the N-type silicon regions and to the P-type emitter regions, the conductive contacts to the N-type silicon regions formed in the contact openings, and the conductive contacts to the P-type emitter regions formed in direct contact with the P-type amorphous silicon layer of the P-type emitter regions.

2 . The method of claim 1 , wherein forming the P-type amorphous silicon layer comprises depositing P-type amorphous silicon by plasma-enhanced chemical vapor deposition (PECVD) at a temperature below approximately 400 degrees Celsius.

3 . The method of claim 1 , wherein forming the P-type amorphous silicon layer comprises forming a P-type amorphous silicon layer having a total hydrogen concentration approximately in the range of 5-20% of total film composition, and having a total phosphorous dopant concentration approximately in the range of 1E19-5E20 atoms/cm3, and to a thickness approximately in the range of 5-50 nanometers.

4 . A method of fabricating a solar cell, the method comprising:

providing a semiconductor substrate having a light-receiving surface and a back surface, the back surface below the light-receiving surface;

forming an N-type emitter region on the back surface of the semiconductor substrate, wherein the N-type emitter region is a planar layer;

forming a P-type emitter region on the back surface of the semiconductor substrate, the P-type emitter region comprising polycrystalline silicon having hydrogen therein, and the P-type emitter region electrically insulated and physically isolated from the N-type emitter region by a single dielectric material, the single dielectric material in direct physical contact with the P-type emitter region and with the N-type emitter region, and the single dielectric material confined to sidewalls of the N-type emitter region, wherein the P-type emitter region is a non-planar layer, and wherein the P-type emitter region has an uppermost surface above an uppermost surface of the N-type emitter region, and the P-type emitter region has a bottommost surface below a bottommost surface of the N-type emitter region;

forming a passivation layer on the P-type emitter region but not on the N-type emitter region, the passivation layer comprising amorphous silicon having hydrogen therein, the passivation layer covering an entirety of a side of the P-type emitter region opposite the semiconductor substrate;

forming a first conductive contact structure electrically connected to and in direct contact with the N-type emitter region; and

forming a second conductive contact structure electrically connected to the P-type emitter region and in direct contact with the passivation layer, wherein the second conductive contact structure has an uppermost surface below the uppermost surface of the N-type emitter region, wherein the second conductive contact is physically separated from an entirety of the P-type emitter region by the passivation layer.

5 . The method of claim 4 , wherein a total composition of the amorphous silicon has a total hydrogen concentration approximately in the range of 5-20% of total film composition.

6 . The method of claim 4 , wherein the passivation layer has a thickness approximately in the range of 5-50 nanometers.

7 . A method of fabricating a back contact solar cell, the method comprising:

providing a semiconductor substrate having a light-receiving surface and a back surface, the back surface below the light-receiving surface;

forming an N-type polycrystalline silicon emitter region on a first thin dielectric layer on the back surface of the semiconductor substrate, wherein the N-type polycrystalline silicon emitter region is a planar layer;

forming a P-type polycrystalline silicon emitter region on a second thin dielectric layer in a trench formed in the back surface of the semiconductor substrate, the P-type polycrystalline silicon emitter region having hydrogen therein, and the P-type polycrystalline silicon emitter region electrically insulated and physically isolated from the N-type polycrystalline silicon emitter region by a single third thin dielectric layer laterally directly between and in physical contact with both the N-type and the P-type polycrystalline silicon emitter regions, and the single third thin dielectric layer confined to sidewalls of the N-type polycrystalline silicon emitter region, wherein the P-type polycrystalline silicon emitter region is a non-planar layer, and wherein the P-type polycrystalline silicon emitter region has an uppermost surface above an uppermost surface of the N-type polycrystalline silicon emitter region, and the P-type emitter polycrystalline silicon region has a bottommost surface below a bottommost surface of the N-type polycrystalline silicon emitter region;

forming a P-type silicon layer on the P-type polycrystalline silicon emitter region but not on the N-type polycrystalline silicon emitter region, the P-type silicon layer comprising amorphous silicon having hydrogen therein, the P-type silicon layer covering an entirety of a side of the P-type polycrystalline silicon emitter region opposite the semiconductor substrate;

forming a first conductive contact structure electrically connected to and in direct contact with the N-type polycrystalline silicon emitter region; and

forming a second conductive contact structure electrically connected to the P-type polycrystalline silicon emitter region and in direct contact with the P-type silicon layer, wherein the second conductive contact structure has an uppermost surface below the uppermost surface of the N-type polycrystalline silicon emitter region, wherein the second conductive contact is physically separated from an entirety of the P-type polycrystalline silicon emitter region by the P-type silicon layer.

8 . The method of claim 7 , wherein the P-type silicon layer is further over, but not in contact with, the N-type polycrystalline silicon emitter region.

9 . The method of claim 7 , wherein a total composition of the amorphous silicon has a total hydrogen concentration approximately in the range of 5-20% of total film composition.

10 . The method of claim 7 , wherein the P-type silicon layer has a thickness approximately in the range of 5-50 nanometers.

11 . The method of claim 10 , wherein the P-type polycrystalline silicon emitter region has a thickness of approximately 30 nanometers, and the P-type silicon layer has a thickness of approximately 20 nanometers.

12 . The method of claim 7 , further comprising:

forming an insulator layer on the N-type polycrystalline silicon emitter region, wherein the first conductive contact structure is through the insulator layer, and wherein a portion of the P-type polycrystalline silicon emitter region and a portion of the P-type silicon layer overlap the insulator layer.

13 . The method of claim 7 , wherein the trench has a texturized surface.

14 . The method of claim 7 , further comprising:

forming a fourth thin dielectric layer on the light-receiving surface of the semiconductor substrate;

forming a polycrystalline silicon layer on the fourth thin dielectric layer; and

forming an anti-reflective coating (ARC) layer on the polycrystalline silicon layer.

15 . The method of claim 7 , wherein the semiconductor substrate is a P-type monocrystalline silicon substrate, and wherein all of the first, second and third thin dielectric layers comprise silicon dioxide.