FAST RECOVERY VOLTAGE REGULATOR
According to an embodiment, a linear voltage regulator is proposed. The regulator includes a voltage source circuit that provides a first voltage at its output terminal. An output transistor having a control terminal is coupled to the output terminal of the voltage source circuit to receive the first voltage. A first current path terminal of the output transistor is couplable to a load and provides a regulated output voltage to the load based on the first voltage. A feedback loop circuit includes sense circuitry to sense current sourced by the output transistor. The circuitry is coupled to a second current path terminal of the output transistor, and a second transistor is configured as a current mirror with the sense circuitry. The second transistor is coupled to the load, wherein the current mirror has a ratio of 1:M, where M is a number normally greater than or equal to 1.
1 . A linear voltage regulator, comprising:
a voltage source circuit configured to provide a first voltage at an output terminal of the voltage source circuit;
an output transistor having a control terminal coupled to the output terminal of the voltage source circuit and configured to receive the first voltage, a first current path terminal of the output transistor couplable to a load and configured to provide a regulated output voltage to the load based on the first voltage; and
a feedback loop circuit comprising:
sense circuitry comprising a feedback transistor configured to sense current sourced by the output transistor, the sense circuitry coupled to a second current path terminal of the output transistor, and
a second transistor configured as a current mirror with the feedback transistor, the second transistor coupled to the load, wherein the current mirror has a ratio of 1:M, where Mis a number normally greater than or equal to 1.
2 . The linear voltage regulator of claim 1 , wherein the feedback loop circuit further comprises a capacitor coupled between the second current path terminal of the output transistor and the load.
3 . The linear voltage regulator of claim 1 , further comprising:
a bypass capacitor coupled between a supply voltage and the load; and
a current generator coupled between the supply voltage and the load.
4 . The linear voltage regulator of claim 1 , wherein the feedback loop circuit further comprises a current generator coupled in parallel to the feedback transistor.
5 . The linear voltage regulator of claim 1 , wherein the output transistor is a PNP-type bipolar junction transistor (BJT) or a p-channel metal-oxide-semiconductor field effect transistor (MOSFET).
6 . The linear voltage regulator of claim 1 , wherein the feedback transistor and the second transistor are NPN bipolar junction transistors (BJTs) or n-channel metal-oxide-semiconductor field effect transistors (MOSFETs).
7 . The linear voltage regulator of claim 1 , wherein the voltage source circuit comprises a reference current generator and a reference resistor, wherein, during steady state, a reference current generated by the reference current generator flows through the reference resistor to generate a reference voltage, and wherein the regulated output voltage equals a voltage across the reference resistor during the steady state.
8 . A linear voltage regulator, comprising:
a voltage source circuit configured to provide a first voltage at an output terminal of the voltage source circuit;
a plurality of output transistors, each output transistor having a control terminal coupled to the output terminal of the voltage source circuit and configured to receive the first voltage, a first current path terminal of each output transistor configured to provide a respective regulated output voltage based on the first voltage to a respective stage of a complimentary metal-oxide-semiconductor (CMOS) logic chain, wherein the CMOS logic chain comprises a plurality of consecutive CMOS logic stages; and
a plurality of feedback loop circuits, each feedback loop circuit comprising:
a feedback transistor configured in a transdiode configuration and coupled to a second current path terminal of an associated output transistor, and
a second transistor configured as a current mirror with the feedback transistor, the second transistor couplable to the respective stage of the CMOS logic chain coupled with the associated output transistor, wherein the current mirror has a ratio of 1:M, where M is an integer greater than or equal to 1.
9 . The linear voltage regulator of claim 8 , wherein the CMOS logic chain drives an output digital-to-analog converter (DAC) in a write circuit for a hard disk drive pre-amplifier.
10 . The linear voltage regulator of claim 8 , wherein a count of output transistors in the linear voltage regulator equals a total number of stages of the CMOS logic chain.
11 . The linear voltage regulator of claim 8 , wherein a total number of stages of the CMOS logic chain is set based on a propagation delay of the CMOS logic chain and a target bit-time.
12 . The linear voltage regulator of claim 8 , wherein each feedback loop circuit further comprises a capacitor coupled between the second current path terminal of the associated output transistor and the respective stage of the CMOS logic chain.
13 . The linear voltage regulator of claim 8 , wherein each output transistor is a PNP-type bipolar junction transistor (BJT) or a p-channel metal-oxide-semiconductor field effect transistor (MOSFET).
14 . The linear voltage regulator of claim 8 , wherein each feedback transistor and each second transistor are NPN bipolar junction transistors (BJTs) or n-channel metal-oxide-semiconductor field effect transistors (MOSFETs).
15 . A write circuit for writing data to a hard disk drive, the write circuit comprising:
an output digital-to-analog converter (DAC);
a complimentary metal-oxide-semiconductor (CMOS) logic chain configured to drive the DAC, the CMOS logic chain comprising a plurality of consecutive CMOS logic sets;
a linear voltage regulator, comprising:
a voltage source circuit configured to provide a first voltage at an output terminal of the voltage source circuit;
a plurality of output transistors, each output transistor having a control terminal coupled to the output terminal of the voltage source circuit and configured to receive the first voltage, a first current path terminal of each output transistor configured to provide a respective regulated output voltage based on the first voltage to a respective stage of the plurality of consecutive CMOS logic sets; and
a plurality of feedback loop circuits, each feedback loop circuit comprising:
a feedback transistor configured in a transdiode configuration and coupled to a second current path terminal of an associated output transistor, and
a second transistor configured as a current mirror with the feedback transistor, the second transistor couplable to the respective stage of the CMOS logic chain coupled with the associated output transistor.
16 . The write circuit of claim 15 , wherein a count of output transistors in the linear voltage regulator equals a total number of stages of the plurality of consecutive CMOS logic sets.
17 . The write circuit of claim 15 , wherein a total number of stages of the plurality of consecutive CMOS logic sets is set based on a propagation delay of the CMOS logic chain and a target bit-time.
18 . The write circuit of claim 15 , wherein each output transistor is a PNP-type bipolar junction transistor (BJT) or a p-channel metal-oxide-semiconductor field effect transistor (MOSFET).
19 . The write circuit of claim 15 , wherein each feedback transistor and each second transistor are NPN bipolar junction transistors (BJTs) or p-channel metal-oxide-semiconductor field effect transistors (MOSFETs).
20 . The write circuit of claim 15 , wherein the linear voltage regulator further comprises:
a plurality of bypass capacitors coupled between a supply voltage and the respective stage of the CMOS logic chain; and
a current generator coupled between the supply voltage and the respective stage of the CMOS logic chain.