METHOD OF FABRICATING SUPER-JUNCTION BASED VERTICAL GALLIUM NITRIDE JFET AND MOSFET POWER DEVICES

1 . A vertical metal oxide semiconductor field effect transistor (MOSFET) device comprising:

a substrate characterized by a first conductivity type;

a first III-nitride layer coupled to the substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type;

first trenches within the first III-nitride layer;

a second III-nitride structure formed within the first trenches, wherein the second III-nitride structure is characterized by a second dopant concentration and a second conductivity type opposite to the first conductivity type;

a third III-nitride layer coupled to the first III-nitride layer and the second III-nitride structure, wherein the third III-nitride layer is characterized by the second conductivity type;

a fourth III-nitride layer coupled to the third III-nitride layer, wherein the fourth III-nitride layer is characterized by the first conductivity type;

second trenches within the third III-nitride layer and the fourth III-nitride layer, wherein the second trenches expose a first portion of the first III-nitride layer;

a gate dielectric within the second trenches, wherein the gate dielectric is coupled to the fourth III-nitride layer, the third III-nitride layer, and the first portion of the first III-nitride layer;

a gate conductor within the second trenches, wherein the gate conductor is adjacent to the gate dielectric; and

a source conductor coupled to an upper portion of the fourth III-nitride layer.

2 . The vertical MOSFET device of claim 1 , wherein:

the second dopant concentration is substantially equal to the first dopant concentration.

3 . The vertical MOSFET device of claim 1 , wherein:

the substrate comprises a III-nitride substrate;

the first III-nitride layer comprises n-type doped GaN;

the second III-nitride structure comprises p-type doped GaN;

the first dopant concentration is in a range from about 1×10 16 atoms/cm 3 to about 1×10 17 atoms/cm 3 ; and

the second dopant concentration is in range from about 1×10 16 atoms/cm 3 to about 1×10 17 atoms/cm 3 .

4 . The vertical MOSFET of claim 3 , wherein:

the fourth III-nitride layer comprises n-type doped GaN with a dopant concentration in the range from about 1×10 17 atoms/cm 3 to about 1×10 18 atoms/cm 3 .

5 . The vertical MOSFET of claim 1 , wherein:

the first III-nitride layer comprises a thickness in a range from about 5 μm to about 20 μm.

6 . The vertical MOSFET device of claim 1 , wherein:

the gate dielectric is conformal to a sidewall and bottom wall of each of the second trenches.

7 . The vertical MOSFET device of claim 1 , wherein:

the gate dielectric comprises multiple layers of individual dielectrics.

8 . The vertical MOSFET device of claim 7 , wherein:

each layer of the multiple layers of individual dielectrics comprises a unique dielectric.

9 . The vertical MOSFET device of claim 7 , wherein:

a first dielectric of the individual dielectrics comprises silicon nitride; and

a second dielectric of the individual dielectrics comprises silicon oxide.

10 . The vertical MOSFET of claim 1 , wherein:

the gate dielectric comprises aluminum oxide.

11 . The vertical MOSFET device of claim 1 , wherein:

the gate conductor comprises a refractory metal.

12 . A vertical metal oxide semiconductor field effect transistor (MOSFET) device comprising:

a substrate characterized by a first conductivity type;

a first III-nitride layer coupled to the substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type;

first trenches within the first III-nitride layer;

a second III-nitride structure formed within the first trenches, wherein the second III-nitride structure is characterized by a second dopant concentration and a second conductivity type opposite to the first conductivity type;

a third III-nitride layer coupled to the first III-nitride layer and the second III-nitride structure, wherein the third III-nitride layer is characterized by the second conductivity type;

a fourth III-nitride layer coupled to the third III-nitride layer, wherein the fourth III-nitride layer is characterized by the first conductivity type;

second trenches within the third III-nitride layer and the fourth III-nitride layer, wherein the second trenches expose a first portion of the first III-nitride layer;

a gate dielectric within the second trenches, wherein the gate dielectric is coupled to the fourth III-nitride layer, the third III-nitride layer, and the first portion of the first III-nitride layer;

a gate conductor within the second trenches, wherein the gate conductor is adjacent to the gate dielectric; and

a source conductor coupled to an upper portion of the fourth III-nitride layer,

wherein:

the second dopant concentration is substantially equal to the first dopant concentration to provide a charge balance structure.

13 . The vertical MOSFET device of claim 12 , wherein:

the gate dielectric is conformal to a sidewall and bottom wall of each of the second trenches.

14 . The vertical MOSFET device of claim 12 , wherein:

the gate dielectric comprises multiple layers of individual dielectrics.

15 . The vertical MOSFET device of claim 14 , wherein:

one of the multiple layers of individual dielectrics comprises silicon nitride or silicon oxide.

16 . A method for fabricating a vertical metal oxide semiconductor field effect transistor (MOSFET) device comprising:

providing a substrate characterized by a first conductivity type;

providing a first III-nitride layer coupled to the substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type;

providing first trenches within the first III-nitride layer;

providing a second III-nitride structure formed within the first trenches, wherein the second III-nitride structure is characterized by a second dopant concentration and a second conductivity type opposite to the first conductivity type, wherein the second dopant concentration is substantially equal to the first dopant concentration;

providing a third III-nitride layer coupled to the first III-nitride layer and the second III-nitride structure, wherein the third III-nitride layer is characterized by the second conductivity type;

providing a fourth III-nitride layer coupled to the third III-nitride layer, wherein the fourth III-nitride layer is characterized by the first conductivity type;

providing second trenches within the third III-nitride layer and the fourth III-nitride layer, wherein the second trenches expose a first portion of the first III-nitride layer;

providing a gate dielectric within the second trenches, wherein the gate dielectric is coupled to the fourth III-nitride layer, the third III-nitride layer, and the first portion of the first III-nitride layer;

providing a gate conductor within the second trenches, wherein the gate conductor is adjacent to the gate dielectric; and

providing a source conductor coupled to an upper portion of the fourth III-nitride layer.

17 . The method of claim 16 , wherein:

providing the substrate comprises providing a III-nitride substrate.

18 . The method of claim 16 , wherein:

providing the gate dielectric comprises depositing a silicon nitride gate dielectric using a PECVD process at a temperature of about 300° C.

19 . The method of claim 16 , wherein:

providing the gate dielectric comprises depositing a aluminum oxide gate dielectric using an ALD process.

20 . The method of claim 16 , wherein:

providing the first III-nitride layer comprises providing an n-type doped GaN layer;

providing the second III-nitride structure comprises p-type doped GaN structure using an MOCVD process; and

the first dopant concentration and the second dopant concentration are in a range from about 1×10 16 atoms/cm 3 to about 1×10 17 atoms/cm 3 .