IP Library Patent Application 18781998
Patent Application
App. No. 18/781,998

Chip with Top Metal Pad Pitch Adjustment

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Quick Facts
Patent No.
US None
App. No.
18/781,998
Abstract

Methods, systems, and apparatuses for a package with top metal pad pitch adjustment are described. A first portion of an integrated circuit (e.g., including transistors and other devices) may have a first pitch associated with internal connections. The first pitch may not align with the pitch of a desired external connection. Accordingly, a set of masks may be used to add a second portion of an integrated circuit (e.g., metal wiring) to the integrated circuit such that the integrated circuit obtains a second pitch, different than the first pitch. The first portion of the integrated circuit may be consistent across one or more integrated circuits while the second portion of the integrated circuit may be customizable for the desired external connections associated with that integrated circuit.

Claims (67)

1 . A method of packaging an integrated circuit comprising:

forming a set of devices of the integrated circuit;

forming a set of internal connections of the integrated circuit that are coupled to the set of devices of the integrated circuit;

selecting a set of masks from a library of sets of masks;

forming a set of metal wiring layers of the integrated circuit using the set of masks; and

coupling a set of external connections of the integrated circuit to the set of internal connections via the metal wiring layers;

wherein: (i) the sets of masks in the library of sets of masks are configured to form different sets of metal wiring layers; and (ii) the different sets of metal wiring layers differ in how they connect the internal connections of the integrated circuit to the external connections of the integrated circuit.

2 . The method of claim 1 , wherein:

the set of metal wiring layers leaves a subset of the set of internal connections uncoupled from the set of external connections; and

the different sets of metal wiring layers differ in how many of the internal connections in the set of internal connections are uncoupled from the set of external connections.

3 . The method of claim 1 , wherein:

the set of external connections are provided as part of a package for the integrated circuit.

4 . The method of claim 3 , wherein:

the set of metal wiring layers form a set of leads that couple to the external connections; and

a pitch of the set of leads is equal to a pitch of the external connections on the package.

5 . An integrated circuit comprising:

a set of devices;

a set of internal connections that are coupled to the set of devices and that have a first pitch, wherein the set of internal connections are a set of metal layer pads;

a set of external connections that are coupled to the set of internal connections and that have a second pitch; and

a set of metal wiring layers of the integrated circuit that couple the set of internal connections to the set of external connections;

wherein a subset of the set of internal connections are not connected to the set of external connections.

6 . The integrated circuit of claim 5 , wherein:

the subset of the set of internal connections are not connected to any of the metal wiring layers in the set of metal wiring layers.

7 . The integrated circuit of claim 5 , wherein:

the set of external connections are package contacts.

8 . The integrated circuit of claim 5 , wherein:

the set of external connections are one of solder balls, bumps, pillars, leads.

9 . The integrated circuit of claim 5 , further comprising:

a second set of external connections having a third pitch, wherein the set of metal wiring layers of the integrated circuit couple the set of internal connections to the second set of external connections.

10 . The integrated circuit of claim 9 , further comprising:

the set of internal connections cover a periphery of the integrated circuit;

the set of external connections is on a first side of the integrated circuit; and

the second set of external connections is on a second side of the integrated circuit.

11 . The integrated circuit of claim 5 , wherein:

the integrated circuit is a chiplet;

the set of devices are transistors; and

the first pitch and the second pitch differ by a factor of two or more.

12 . A method comprising:

forming a first set of devices of a first integrated circuit;

forming a first set of internal connections of the first integrated circuit that are coupled to the first set of devices of the first integrated circuit;

selecting a first set of masks from a library of sets of masks based at least in part on a first set of external connections;

forming a first set of metal wiring layers of the first integrated circuit using the first set of masks;

forming a second set of devices of a second integrated circuit, wherein the second set of devices is in a same configuration as a configuration of the first set of devices;

forming a second set of internal connections of the second integrated circuit that are coupled to the second set of devices of the second integrated circuit;

selecting a second set of masks from the library of sets of masks based at least in part on a second set of external connections, wherein the second set of masks is different than the first set of masks and the second set of external connections has a different configuration than a configuration of the first set of external connections; and

forming a second set of metal wiring layers of the second integrated circuit using the second set of masks, wherein the second integrated circuit has a configuration that is different than a configuration of the first set of metal wiring layers.

13 . The method of claim 12 , further comprising:

coupling the first set of external connections of the first integrated circuit to the first set of internal connections via the first set of metal wiring layers; and

coupling the second set of external connections of the second integrated circuit to the second set of internal connections via the second set of metal wiring layers.

14 . The method of claim 13 , wherein forming the first set of metal wiring layers comprises leaving a subset of the first set of internal connections uncoupled from the first set of external connections in a first metal wiring configuration.

15 . The method of claim 14 , wherein forming the second set of metal wiring layers comprises leaving a subset of the second set of internal connections uncoupled from the second set of external connections in a second metal wiring configuration, a quantity of the subset of the first set of internal connections uncoupled from the first set of external connections being different than a quantity of the subset of the second set of internal connections uncoupled from the second set of external connections.

16 . The method of claim 12 , wherein:

the first set of external connections is associated with a first package; and

the second set of external connections is associated with a second package.

17 . The method of claim 16 , wherein:

the first package is different than the second package.

18 . The method of claim 12 , wherein:

the first set of external connections are one of solder balls, bumps, pillars, leads; and

the second set of external connections are one of solder balls, bumps, pillars, leads.

19 . The method of claim 12 , wherein:

the first and second integrated circuits are chiplets; and

the first and second sets of devices are transistors.

20 . The method of claim 12 , wherein:

the first set of internal connections are associated with a first pitch, the second set of internal connections are associated with a second pitch, the first set of external connections are associated with a third pitch, and the second set of external connections are associated with a fourth pitch;

the first pitch is different than the third pitch;

the second pitch is different than the fourth pitch; and

the third pitch is different than the fourth pitch.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2025
From: ALON, ELAD
To: TENSTORRENT AI ULC
Reel/Frame 072078/0138 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2025
From: NABOVATI, AYDIN; PFEIFFENBERGER, ALEXANDER HELMUT; BAILEY, DANIEL WILLIAM
To: TENSTORRENT AI ULC
Reel/Frame 070234/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2024
From: NABOVATI, AYDIN; PFEIFFENBERGER, ALEXANDER HELMUT; BAILEY, DANIEL WILLIAM
To: TENSTORRENT INC.
Reel/Frame 068154/0460 →