PROCESSED STACKED DIES
Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.
1 . A bonded structure, comprising:
a first element comprising a first semiconductor element and a first dielectric layer, wherein the first dielectric layer comprises a first direct bonding surface; and
a second singulated element comprising a second semiconductor element and a second dielectric layer without embedded conductive layers, the second dielectric layer disposed on the second semiconductor element, wherein the second dielectric layer comprises a second direct bonding surface, the second direct bonding surface directly bonded to the first direct bonding surface without an adhesive;
wherein an upper surface of the second singulated element is recessed such that an area of a bonded portion of the upper surface of the second singulated element is less than an area of a cross-section of the widest portion of the second singulated element.
2 . The bonded structure of claim 1 , wherein the upper surface creates an undercut between the first element and the second singulated element.
3 . The bonded structure of claim 2 , wherein the undercut extends into the second semiconductor element such that the second semiconductor element is exposed at a periphery of the second singulated element.
4 . The bonded structure of claim 1 , wherein the first and second direct bonding surfaces include a substantially planar surface.
5 . The bonded structure of claim 1 , wherein the second direct bonding surface includes a substantially planar oxide layer, and wherein at least a portion of the substantially planar oxide layer at one or more edges of the second dielectric layer is recessed or removed.
6 . The bonded structure of claim 1 , wherein the second semiconductor element has an undercut comprising a recess at a periphery of the second semiconductor element corresponding to a recessed portion of the upper surface.
7 . The bonded structure of claim 1 , further comprising an undercut at a periphery of the first semiconductor element, an undercut at a periphery of the second semiconductor element, or an undercut at a periphery of the first semiconductor element and an undercut at a periphery of the second semiconductor element.
8 . The bonded structure of claim 1 , wherein the second semiconductor element of the second singulated element has a recess at a portion of the second semiconductor element corresponding to the recess at the portion of the upper surface.
9 . The bonded structure of claim 1 , wherein the upper surface comprises a sloped profile.
10 . The bonded structure of claim 9 , wherein the sloped profile extends into the second semiconductor element.
11 . The bonded structure of claim 1 , wherein the second singulated element consists of the second semiconductor element and the second dielectric layer.