Hardware Algorithm for Complex-Valued Exponentiation and Logarithm Using Simplified Sub-Steps
A method of generating complex exponentiation and logarithms in hardware is described that uses half the number of bits of lookup tables as the state-of-the-art. By splitting up each of the iterations into more simplified stages or using more iterations, the amount of precomputed information that must be held by the circuitry is reduced. This allows synthesis tools to take this more succinct logical description of the algorithm and make it into efficient gate level logic for fabrication into more compact integrated circuitry.
1 . A system comprising:
a hardware component having at least one input and at least one output;
wherein the hardware component implements a switchable complex-valued unit having a to-logarithm functionality and a to-exponential functionality;
wherein the at least one input and the at least one output are complex valued;
wherein shift-and-add processes are applied to values in the hardware component that effect a separable multiplication of: i) the at least one input; ii) (1+c); and (1+di);
wherein “c” is a real value and “di” is an imaginary value.
2 . The system of claim 1 , wherein a logarithm process implemented by the unit is an affine logarithm process; and wherein an exponential processes implemented by the unit are an affine exponential process.
3 . The system of claim 2 , wherein the relation:
2
tan
-
1
2
-
p
π
≈
1
2
log
2
1
+
2
-
p
,
is used to approximate a lookup value of an arctangent expression as an existing lookup value of a binary logarithm expression and a smaller delta table.
4 . The system of claim 2 , wherein an imaginary part of the input in the affine logarithm process is tested and, if less than −½ or greater than or equal to +½, rotated by 45 degrees prior to an iteration.
5 . The system of claim 1 , wherein the to-logarithm functionality completes a division of an auxiliary value in parallel on an iteration.
6 . The system of claim 1 , wherein the to-exponential functionality completes a division of an auxiliary value in parallel on an iteration.
7 . The system of claim 1 , wherein the to-logarithm functionality conducts an iteration test on a value that is an existing value subtracted by +1.
8 . The system of claim 1 , wherein the to-exponential functionality conducts an iteration test on a value that is an existing value subtracted by +1.
9 . The system of claim 1 , wherein “c” is also a non-zero value and “di” is also a non-zero value.
10 . The system of claim 9 , wherein a logarithm process implemented by the unit is an affine logarithm process; and wherein an exponential processes implemented by the unit are an affine exponential process.
11 . The system of claim 10 , wherein the relation:
2
tan
-
1
2
-
p
π
≈
1
2
log
2
1
+
2
-
p
,
is used to approximate a lookup value of an arctangent expression as an existing lookup value of a binary logarithm expression and a smaller delta table.
12 . The system of claim 10 , wherein an imaginary part of the input in the affine logarithm process is tested and, if less than −½ or greater than or equal to +½, rotated by 45 degrees prior to an iteration.
13 . The system of claim 9 , wherein the to-logarithm functionality completes a division of an auxiliary value in parallel on an iteration.
14 . The system of claim 9 , wherein the to-exponential functionality completes a division of an auxiliary value in parallel on an iteration.
15 . The system of claim 9 , wherein the to-logarithm functionality conducts an iteration test on a value that is an existing value subtracted by +1.
16 . The system of claim 9 , wherein the to-exponential functionality conducts an iteration test on a value that is an existing value subtracted by +1.
17 . The system of claim 9 , wherein when iterations of the shift-and-add processes are applied to the values in the hardware component, an aggregation of the values in the hardware component substantially follow a Fibonacci sequence.