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1 . A buffer circuit for a communication interface, the buffer circuit comprising:

a charge pump configured to boost a supply voltage supplied to the buffer circuit and generate a boosted supply voltage at an output terminal of the charge pump;

a first resistor;

a first capacitor having a first terminal coupled to an output terminal of the buffer circuit;

a first p-channel transistor having a source terminal coupled to the supply voltage, a drain terminal of the first p-channel transistor coupled to a first terminal of the first resistor, a gate terminal of the first p-channel transistor coupled to an input of the buffer circuit;

a first n-channel transistor having a source terminal coupled to reference ground, a drain terminal of the first n-channel transistor coupled to a second terminal of the first resistor, a gate terminal of the first n-channel transistor coupled to the input of the buffer circuit;

a second n-channel transistor having a source terminal coupled to reference ground, a gate terminal of the second n-channel transistor coupled to the second terminal of the first resistor;

a third n-channel transistor having a source terminal coupled to the drain terminal of the second n-channel transistor, a drain terminal of the third n-channel transistor coupled to the output terminal of the buffer circuit, a gate terminal of the third n-channel transistor coupled to the output terminal of the charge pump and configured to receive the boosted supply voltage;

a fourth n-channel transistor having a source terminal coupled to reference ground, a drain terminal of the fourth n-channel transistor coupled to a second terminal of the first capacitor, a gate terminal of the fourth n-channel transistor coupled to the gate terminal of the first n-channel transistor; and

a fifth n-channel transistor having a gate terminal coupled to its drain terminal and the second terminal of the first resistor, the source terminal of the fifth n-channel transistor coupled to the second terminal of the first capacitor.

2 . The buffer circuit of claim 1 , further comprising a filtering circuit coupled between the charge pump and the gate terminal of the third n-channel transistor, the filtering circuit configured to:

reduce ripples at the output terminal of the charge pump from the gate terminal of the third n-channel transistor; and

reduce noise generated by switching of an SDA signal of the buffer circuit.

3 . The buffer circuit of claim 1 , wherein the communication interface is an integrated circuit (I 2 C) communication interface, and wherein the buffer circuit is arranged on a serial data line of a communication bus of the P 2 C communication interface.

4 . The buffer circuit of claim 1 , wherein the first p-channel transistor, the first n-channel transistor, the second n-channel transistor, the fourth n-channel transistor, and the fifth n-channel transistor are low-voltage transistors having a threshold voltage between 0.4 and 0.6V inclusive.

5 . The buffer circuit of claim 1 , wherein the third n-channel transistor is a high-voltage transistor with a threshold voltage between 0.8 and 1V inclusive.

6 . The buffer circuit of claim 1 , wherein the supply voltage is less than 1.4V, and wherein the boosted supply voltage is greater than 2.5V.

7 . The buffer circuit of claim 1 , wherein the supply voltage is 1.2V, wherein the first p-channel transistor, the first n-channel transistor, the second n-channel transistor, the fourth n-channel transistor, and the fifth n-channel transistor are low-voltage transistors having a threshold voltage between 0.4 and 0.6V inclusive, and wherein the third n-channel transistor is a high-voltage transistor with a threshold voltage between 0.8 and 1V inclusive.

8 . A buffer circuit for a communication interface, the buffer circuit comprising:

a charge pump configured to boost a supply voltage supplied to the buffer circuit and generate a boosted supply voltage at an output terminal of the charge pump;

a reference current source configured to generate a reference current;

a mirror p-channel transistor having a gate terminal coupled to the reference current source;

a reference p-channel transistor having a source terminal coupled to the supply voltage, a gate terminal of the reference p-channel transistor coupled to its drain terminal and the reference current source;

a first capacitor having a first terminal coupled to an output terminal of the buffer circuit;

a first p-channel transistor having a source terminal coupled to the supply voltage, a drain terminal of the first p-channel transistor coupled to a source terminal of the mirror p-channel transistor, a gate terminal of the first p-channel transistor coupled to an input of the buffer circuit;

a first n-channel transistor having a source terminal coupled to reference ground, a drain terminal of the first n-channel transistor coupled to a drain terminal of the mirror p-channel transistor, a gate terminal of the first n-channel transistor coupled to the input of the buffer circuit;

a second n-channel transistor having a source terminal coupled to reference ground, a gate terminal of the second n-channel transistor coupled to the drain terminal of the mirror p-channel transistor;

a third n-channel transistor having a source terminal coupled to the drain terminal of the second n-channel transistor, a drain terminal of the third n-channel transistor coupled to the output terminal of the buffer circuit, a gate terminal of the third n-channel transistor coupled to the output terminal of the charge pump and configured to receive the boosted supply voltage;

a fourth n-channel transistor having a source terminal coupled to reference ground, a drain terminal of the fourth n-channel transistor coupled to a second terminal of the first capacitor, a gate terminal of the fourth n-channel transistor coupled to the gate terminal of the first n-channel transistor; and

a fifth n-channel transistor having a gate terminal coupled to its drain terminal and the drain terminal of the mirror p-channel transistor, the source terminal of the fifth n-channel transistor coupled to the second terminal of the first capacitor.

9 . The buffer circuit of claim 8 , further comprising a filtering circuit coupled between the charge pump and the gate terminal of the third n-channel transistor, the filtering circuit configured to reduce ripples at the output terminal of the charge pump from the gate terminal of the third n-channel transistor.

10 . The buffer circuit of claim 8 , wherein the communication interface is an integrated circuit (I 2 C) communication interface, and wherein the buffer circuit is arranged on a serial data line of a communication bus of the I 2 C communication interface.

11 . The buffer circuit of claim 8 , wherein the mirror p-channel transistor, the reference p-channel transistor, the first p-channel transistor, the first n-channel transistor, the second n-channel transistor, the fourth n-channel transistor, and the fifth n-channel transistor are low-voltage transistors having a threshold voltage between 0.4 and 0.6V inclusive.

12 . The buffer circuit of claim 8 , wherein the third n-channel transistor is a high-voltage transistor with a threshold voltage between 0.8 and 1V inclusive.

13 . The buffer circuit of claim 8 , wherein the supply voltage is less than 1.4V, and wherein the boosted supply voltage is greater than 2.5V.

14 . The buffer circuit of claim 8 , wherein the supply voltage is 1.2V, wherein the mirror p-channel transistor, the reference p-channel transistor, the first p-channel transistor, the first n-channel transistor, the second n-channel transistor, the fourth n-channel transistor, and the fifth n-channel transistor are low-voltage transistors having a threshold voltage between 0.4 and 0.6V inclusive, and wherein the third n-channel transistor is a high-voltage transistor with a threshold voltage between 0.8 and 1V inclusive.

15 . A communication system, comprising:

a primary controller comprising a first buffer circuit;

an auxiliary circuit coupled to the primary controller through a communication bus, the auxiliary circuit comprising a second buffer circuit;

wherein the first buffer circuit or the second buffer circuit comprises:

a charge pump configured to boost a supply voltage supplied to the associated buffer circuit and generate a boosted supply voltage at an output terminal of the charge pump;

a first resistor;

a first capacitor having a first terminal coupled to an output terminal of the associated buffer circuit;

a first p-channel transistor having a source terminal coupled to the supply voltage, a drain terminal of the first p-channel transistor coupled to a first terminal of the first resistor, a gate terminal of the first p-channel transistor coupled to an input of the associated buffer circuit;

a first n-channel transistor having a source terminal coupled to reference ground, a drain terminal of the first n-channel transistor coupled to a second terminal of the first resistor, a gate terminal of the first n-channel transistor coupled to the input of the associated buffer circuit;

a second n-channel transistor having a source terminal coupled to reference ground, a gate terminal of the second n-channel transistor coupled to the second terminal of the first resistor;

a third n-channel transistor having a source terminal coupled to the drain terminal of the second n-channel transistor, a drain terminal of the third n-channel transistor coupled to the output terminal of the associated buffer circuit, a gate terminal of the third n-channel transistor coupled to the output terminal of the charge pump and configured to receive the boosted supply voltage;

a fourth n-channel transistor having a source terminal coupled to reference ground, a drain terminal of the fourth n-channel transistor coupled to a second terminal of the first capacitor, a gate terminal of the fourth n-channel transistor coupled to the gate terminal of the first n-channel transistor; and

a fifth n-channel transistor having a gate terminal coupled to its drain terminal and the second terminal of the first resistor, the source terminal of the fifth n-channel transistor coupled to the second terminal of the first capacitor.

16 . The communication system of claim 15 , wherein the first buffer circuit or the second buffer circuit further comprises a filtering circuit coupled between the charge pump and the gate terminal of the third n-channel transistor, the filtering circuit configured to:

reduce ripples at the output terminal of the charge pump from the gate terminal of the third n-channel transistor; and

reduce noise generated by switching of an SDA signal.

17 . The communication system of claim 15 , wherein each of the primary controller and the auxiliary circuit further comprises an electrostatic discharge (ESD) protection circuit configured to provide ESD protection, the ESD protection circuit comprising:

a second capacitor having a first terminal coupled to the communication bus;

a second resistor having a first terminal coupled to a second terminal of the second capacitor, a second terminal of the second resistor coupled to reference ground;

a sixth n-channel transistor having a gate terminal configured to receive a signal corresponding to an operational state of the associated buffer circuit, a source terminal of the sixth n-channel transistor coupled to reference ground; and

a seventh n-channel transistor having a gate terminal coupled to a drain terminal of the sixth n-channel transistor, the second terminal of the second capacitor, and the first terminal of the second resistor, a source terminal of the seventh n-channel transistor coupled to reference ground, and a drain terminal of the seventh n-channel transistor coupled to the output terminal of the charge pump and configured to receive the boosted supply voltage.

18 . The communication system of claim 15 , wherein the communication system is a communication system with an integrated circuit (I 2 C) communication interface, and wherein each buffer circuit is arranged on a serial data line of the communication bus.

19 . The communication system of claim 15 , wherein the first p-channel transistor, the first n-channel transistor, the second n-channel transistor, the fourth n-channel transistor, and the fifth n-channel transistor are low-voltage transistors having a threshold voltage between 0.4 and 0.6V inclusive, and wherein the third n-channel transistor is a high-voltage transistor with a threshold voltage between 0.8 and 1V inclusive.

20 . The communication system of claim 15 , wherein the supply voltage is less than 1.4V, and wherein the boosted supply voltage is greater than 2.5V.