Granted Patent B2

US 12,531,717 · App. 18/793,128 · Granted Jan 20, 2026

Inventors: Davide Nicolo Fortunato (Palermo, IT); Antonino Calcagno (Messina, IT); Gaetano Cosentino (Catania, IT); Marco Vinciguerra (Catania, IT)

Assignee: STMicroelectronics International N.V.

H04L7/033

Abstract

Claims (96)

1 . A phase-locked loop (PLL) circuit comprising:

a voltage-controlled oscillator (VCO) circuit configured to be driven by a control voltage and produce an output periodic signal;

a comparator circuit configured to:

compare the control voltage to a comparison signal;

assert a detection signal in response to the control voltage being higher than the comparison signal; and

de-assert the detection signal in response to the control voltage being lower than the comparison signal; and

a digital logic circuit configured to:

receive the detection signal;

produce the comparison signal;

produce a compensation signal for controlling operation of the VCO circuit;

during a first phase of a VCO compensation procedure, determine and store a value of the comparison signal that corresponds to a current value of the control voltage, and compare the stored value of the comparison signal to a target value to determine whether the control voltage should be increased or decreased; and

during a second phase of the VCO compensation procedure, iteratively change a value of the compensation signal until the control voltage reaches a desired value.

2 . The PLL circuit of claim 1 , wherein the comparator circuit is an analog comparator circuit, and wherein the PLL circuit comprises a digital-to-analog converter circuit configured to receive the comparison signal from the digital logic circuit as a digital comparison signal and to convert the digital comparison signal into a corresponding analog comparison signal that is fed to the analog comparator circuit.

3 . The PLL circuit of claim 2 , wherein, during the first phase of the VCO compensation procedure, the digital logic circuit is configured to:

assign a value of a first variable to the digital comparison signal;

iteratively update the value of the first variable according to a dichotomic search, wherein a direction of each iteration of the dichotomic search is selected as a function of a value of the detection signal; and

store a last updated value of the first variable for subsequent comparison to the target value.

4 . The PLL circuit of claim 3 , wherein the digital logic circuit is configured to wait for an expiration of a first timer between two subsequent updates of the first variable.

5 . The PLL circuit of claim 2 , wherein, during the second phase of the VCO compensation procedure, the digital logic circuit is configured to:

assign the target value to the digital comparison signal; and

gradually change the value of the compensation signal until the detection signal toggles.

6 . The PLL circuit of claim 5 , wherein the digital logic circuit is configured to:

in response to determining that the control voltage should be increased, gradually decrease the value of the compensation signal until the detection signal toggles to a de-asserted state; and

in response to determining that the control voltage should be decreased, gradually increase the value of the compensation signal until the detection signal toggles to an asserted state.

7 . The PLL circuit of claim 1 , wherein the digital logic circuit is configured to wait for an expiration of a second timer between two subsequent changes of the value of the compensation signal.

8 . The PLL circuit of claim 1 , wherein the digital logic circuit is configured to wait for an expiration of a third timer between two subsequent executions of the VCO compensation procedure.

9 . The PLL circuit of claim 1 , wherein the VCO circuit comprises:

a varactor and/or a bank of capacitors controlled by the compensation signal; and

a further digital-to-analog converter circuit configured to convert the compensation signal into an analog compensation signal to control the varactor and/or the bank of capacitors.

10 . The PLL circuit of claim 1 , further comprising:

a phase frequency detector circuit configured to compare a reference periodic signal to a feedback signal produced as a function of the output periodic signal, and produce a phase error signal indicative of a phase error between the reference periodic signal and the feedback signal;

a charge pump circuit configured to receive the phase error signal and produce positive or negative current pulses depending on a polarity of the phase error signal;

a low-pass filter circuit configured to receive the current pulses from the charge pump circuit and produce the control voltage as a function thereof; and

a frequency divider circuit configured to receive the output periodic signal and produce the feedback signal by dividing a frequency of the output periodic signal.

11 . A method of operating a phase-locked loop (PLL) circuit, the method comprising:

driving a voltage-controlled oscillator (VCO) circuit with a control voltage;

generating, by the VCO circuit, an output periodic signal;

comparing, by a comparator circuit, the control voltage to a comparison signal;

de-asserting, by the comparator circuit, a detection signal in response to the control voltage being lower than the comparison signal;

receiving, by a digital logic circuit, the detection signal;

producing, by the digital logic circuit, the comparison signal;

producing, by the digital logic circuit, a compensation signal for controlling operation of the VCO circuit;

during a first phase of a VCO compensation procedure:

determining and storing, by the digital logic circuit, a value of the comparison signal that corresponds to a current value of the control voltage; and

comparing, by the digital logic circuit, the stored value of the comparison signal to a target value to determine that the control voltage should be increased; and

during a second phase of the VCO compensation procedure, iteratively decreasing, by the digital logic circuit, a value of the compensation signal until the control voltage increases to a desired value.

12 . The method of claim 11 , wherein the comparator circuit is an analog comparator circuit, and the method further comprises:

receiving, by a digital-to-analog converter circuit, the comparison signal from the digital logic circuit as a digital comparison signal; and

converting, by the digital-to-analog converter circuit, the digital comparison signal into a corresponding analog comparison signal that is fed to the analog comparator circuit.

13 . The method of claim 12 , further comprising, during the first phase of the VCO compensation procedure:

assigning, by the digital logic circuit, a value of a first variable to the digital comparison signal;

iteratively updating, by the digital logic circuit, the value of the first variable according to a dichotomic search, wherein a direction of each iteration of the dichotomic search is selected as a function of a value of the detection signal; and

storing, by the digital logic circuit, a last updated value of the first variable for subsequent comparison to the target value.

14 . The method of claim 12 , further comprising, during the second phase of the VCO compensation procedure:

assigning, by the digital logic circuit, the target value to the digital comparison signal; and

gradually decreasing, by the digital logic circuit, the value of the compensation signal until the detection signal toggles to a de-asserted state.

15 . The method of claim 11 , further comprising:

comparing, by a phase frequency detector circuit, a reference periodic signal to a feedback signal produced as a function of the output periodic signal;

producing, by the phase frequency detector circuit, a phase error signal indicative of a phase error between the reference periodic signal and the feedback signal;

receiving, by a charge pump circuit, the phase error signal;

producing, by the charge pump circuit, positive or negative current pulses depending on a polarity of the phase error signal;

receiving, by a low-pass filter circuit, the current pulses from the charge pump circuit;

producing, by the low-pass filter circuit, the control voltage as a function thereof;

receiving, by a frequency divider circuit, the output periodic signal; and

producing, by the frequency divider circuit, the feedback signal by dividing a frequency of the output periodic signal.

16 . A method of operating a phase-locked loop (PLL) circuit, the method comprising:

driving a voltage-controlled oscillator (VCO) circuit with a control voltage;

generating, by the VCO circuit, an output periodic signal;

comparing, by a comparator circuit, the control voltage to a comparison signal;

asserting, by the comparator circuit, a detection signal in response to the control voltage being higher than the comparison signal;

receiving, by a digital logic circuit, the detection signal;

producing, by the digital logic circuit, the comparison signal;

producing, by the digital logic circuit, a compensation signal for controlling operation of the VCO circuit;

during a first phase of a VCO compensation procedure:

determining and storing, by the digital logic circuit, a value of the comparison signal that corresponds to a current value of the control voltage; and

comparing, by the digital logic circuit, the stored value of the comparison signal to a target value to determine that the control voltage should be decreased; and

during a second phase of the VCO compensation procedure, iteratively increasing, by the digital logic circuit, a value of the compensation signal until the control voltage decreases to a desired value.

17 . The method of claim 16 , wherein the comparator circuit is an analog comparator circuit, and the method further comprises:

receiving, by a digital-to-analog converter circuit, the comparison signal from the digital logic circuit as a digital comparison signal; and

converting, by the digital-to-analog converter circuit, the digital comparison signal into a corresponding analog comparison signal that is fed to the analog comparator circuit.

18 . The method of claim 17 , further comprising, during the first phase of the VCO compensation procedure:

assigning, by the digital logic circuit, a value of a first variable to the digital comparison signal;

iteratively updating, by the digital logic circuit, the value of the first variable according to a dichotomic search, wherein a direction of each iteration of the dichotomic search is selected as a function of a value of the detection signal; and

storing, by the digital logic circuit, a last updated value of the first variable for subsequent comparison to the target value.

19 . The method of claim 17 , further comprising, during the second phase of the VCO compensation procedure:

assigning, by the digital logic circuit, the target value to the digital comparison signal; and

gradually increasing, by the digital logic circuit, the value of the compensation signal until the detection signal toggles to an asserted state.

20 . The method of claim 16 , further comprising:

comparing, by a phase frequency detector circuit, a reference periodic signal to a feedback signal produced as a function of the output periodic signal;

producing, by the phase frequency detector circuit, a phase error signal indicative of a phase error between the reference periodic signal and the feedback signal;

receiving, by a charge pump circuit, the phase error signal;

producing, by the charge pump circuit, positive or negative current pulses depending on a polarity of the phase error signal;

receiving, by a low-pass filter circuit, the current pulses from the charge pump circuit;

producing, by the low-pass filter circuit, the control voltage as a function thereof;

receiving, by a frequency divider circuit, the output periodic signal; and

producing, by the frequency divider circuit, the feedback signal by dividing a frequency of the output periodic signal.

Assignments (2)

Priority Claims (1)

Continuity (1)

References Cited (9)