SYSTEM AND METHOD FOR REQUESTING MEMORY ACCESS

1 . A computing device comprising:

a bank of processing elements;

a high bandwidth memory module in communication with the bank of processing elements and including a plurality of channels of memory;

a plurality of bridges corresponding to the plurality of channels of memory, each bridge configured to connect a designated channel of the channels of memory to a designated vector of processing elements in the bank and including a bridge controller configured to:

in response to a request for a memory access for a processing operation, perform the memory access to retrieve a data value from the designated channel according to the request; and

provide the data value to a processing element in the designated vector to process according to the processing operation.

2 . The computing device of claim 1 , wherein the bridge controller is configured to:

perform the memory access to retrieve a set of data values from the designated channel according to the request; and

distribute the set of data values to the processing elements in the designated vector to process according to the processing operation.

3 . The computing device of claim 2 , wherein the bridge controller is further configured to generate direct memory access (DMA) descriptors for processing by a DMA module to retrieve the set of data values from the designated channel.

4 . The computing device of claim 3 , wherein the bridge controller is configured to:

generate a first subset of DMA descriptors and send the first subset of DMA descriptors to the DMA module for retrieval; and

while the first subset of DMA descriptors is being processed by the DMA module for retrieval of the data values from the designated channel, generate a second subset of DMA descriptors.

5 . The computing device of claim 1 , wherein the designated vector corresponds to a portion of a column of the processing elements in the bank.

6 . The computing device of claim 1 , further comprising a controller, wherein the controller is configured to:

initiate the processing operation;

send the request for the memory access to the plurality of bridges; and

send a processing instruction to the bank of processing elements to process the data value in accordance with the processing operation upon receipt of the data value.

7 . The computing device of claim 1 , wherein the plurality of bridges are configured to cooperate to assign the memory access request according to the data values stored in the corresponding designated channel.

8 . A method comprising:

initiating, at a controller, a processing operation;

identifying a memory access request to retrieve a target data value;

processing, by a bridge controller of a bridge, the memory access request to retrieve the target data value from a designated channel of a high bandwidth memory connected to the bridge; and

providing the target data value to a processing element in a designated vector connected to the bridge to process according to the processing operation.

9 . The method of claim 8 , wherein:

the memory access request is to retrieve a set of target data values; and

wherein providing the target data value comprising distributing the set of target data values to the processing elements in the designated vector.

10 . The method of claim 9 , wherein processing the memory access request comprises:

generating, by the bridge controller, direct memory access (DMA) descriptors for retrieving the set of target data values by a DMA module from the designated channel.

11 . The method of claim 10 , wherein generating the DMA descriptors comprises:

generating a first subset of DMA descriptors and sending the first subset of DMA descriptors to the designated channel for retrieval; and

generating a second subset of DMA descriptors.

12 . The method of claim 11 , further comprising processing, by the designated channel, the first subset of DMA descriptors to retrieve the target data values in the first subset.

13 . The method of claim 12 , wherein the processing the first subset by the designated channel and the generating the second subset by the DMA module occurs substantially simultaneously.

14 . The method of claim 8 , wherein processing the memory access request comprises: coordinating, by a set of bridges, assignment of the memory access request according to the data values stored in the designated channel.