LEVEL SHIFTING CIRCUIT

1 . A level shifter circuit, comprising:

an input circuit comprising a plurality of low voltage threshold switches and configured to receive an input voltage and to generate a second voltage, wherein the second voltage varies between a first low voltage and a first high voltage;

an output circuit comprising a first plurality of high voltage switches and configured to receive the second voltage and to generate a third voltage, wherein the third voltage varies between the first low voltage and a second high voltage; and

a buffer circuit, the buffer circuit being configured to receive the third voltage and to generate a buffer circuit output voltage, wherein the buffer circuit output voltage varies between a second low voltage and the second high voltage.

2 . The level shifter circuit of claim 1 , wherein the second high voltage is greater than the first low voltage, and wherein the first high voltage is less than the second high voltage.

3 . The level shifter circuit of claim 1 , wherein the second low voltage is greater than the first low voltage.

4 . The level shifter circuit of claim 1 , wherein the second low voltage is equal to the first low voltage.

5 . The level shifter circuit of claim 1 , wherein the output circuit further comprises a second plurality of low voltage switches.

6 . The level shifter circuit of claim 1 , wherein the first high voltage is greater than the first low voltage and is less than the second high voltage.

7 . The level shifter circuit of claim 1 , wherein the buffer circuit comprises a plurality of medium voltage switches.

8 . The level shifter circuit of claim 1 , wherein each P type switch of the output circuit and the buffer circuit is a high voltage switch, and wherein each N type switch of the output circuit and the buffer circuit is either a medium voltage switch or a low voltage switch.

9 . An array circuit, comprising:

an array of devices, wherein a plurality of devices of the array each comprise at least one high voltage switch;

a controller configured to generate a plurality of first control signals for controlling the array of devices; and

an array of level shifters, each level shifter configured to receive one of the first control signals from the controller as an input voltage, to generate one of a plurality of second control signals as a level shifter output voltage, and to provide the level shifter output voltage to one of the devices of the array of devices, wherein the level shifters each comprise:

an input circuit comprising a plurality of low voltage threshold switches and configured to generate a second voltage, wherein the second voltage varies between a first low voltage and a first high voltage;

an output circuit comprising a first plurality of high voltage switches and configured to receive the second voltage and to generate a third voltage, wherein the third voltage varies between the first low voltage and a second high voltage; and

a buffer circuit, the buffer circuit configured to receive the third voltage and to generate a buffer circuit output voltage, wherein the buffer circuit output voltage varies between a second low voltage and the second high voltage.

10 . The array circuit of claim 9 , wherein the second high voltage is greater than the first low voltage, and wherein the first high voltage is less than the second high voltage.

11 . The array circuit of claim 9 , wherein the second low voltage is greater than the first low voltage.

12 . The array circuit of claim 9 , wherein the second low voltage is equal to the first low voltage.

13 . The array circuit of claim 9 , wherein the output circuit comprises a second plurality of low voltage switches.

14 . The array circuit of claim 9 , wherein the first high voltage is greater than the first low voltage and is less than the second high voltage.

15 . The array circuit of claim 9 , wherein the buffer circuit comprises a plurality of medium voltage switches.

16 . The array circuit of claim 9 , wherein each P type switch of the output circuit and the buffer circuit is a high voltage switch, and wherein each N type switch of the output circuit and the buffer circuit is either a medium voltage switch or a low voltage switch.

17 . A method of using a level shifter circuit, the method comprising:

with an input circuit comprising a plurality of low voltage threshold switches:

receiving an input voltage, and

generating a second voltage based in part on the input voltage, wherein the second voltage varies between a first low voltage and a first high voltage;

with an output circuit comprising a plurality of high voltage switches:

receiving the second voltage, and

generating a third voltage based on the second voltage, wherein the third voltage varies between the first low voltage and a second high voltage; and

with a buffer circuit:

receiving the third voltage, and

generating an output voltage based on the third voltage, wherein the output voltage varies between a second low voltage and the second high voltage.

18 . The method of claim 17 , wherein the second high voltage is greater than the first low voltage, and wherein the first high voltage is less than the second high voltage.

19 . The method of claim 17 , wherein the second low voltage is greater than the first low voltage.

20 . The method of claim 17 , wherein the second low voltage is equal to the first low voltage.