Chiplet system and method for communicating between chiplets in chiplet system
The present disclosure relates to a method for communicating between chiplets in a chiplet system. The chiplet system includes a first chiplet and a second chiplet, the first chiplet includes a controller including a protocol layer, and the method includes, by the protocol layer of the first chiplet, receiving first data, by the protocol layer of the first chiplet, receiving conversion information from the second chiplet, and, by the protocol layer of the first chiplet, generating second data based on the received first data and conversion information.
1 . A method for communicating between chiplets in a chiplet system, wherein
the chiplet system includes a first chiplet associated with a first protocol and a second chiplet associated with a second protocol, the chiplet system further including an interface between the first chiplet and the second chiplet,
the first chiplet includes a controller including a protocol layer,
the method comprising:
at the protocol layer of the first chiplet, receiving first data associated with the first protocol;
at the protocol layer of the first chiplet, receiving conversion information including encoding information associated with the second protocol or decoding information associated with the first protocol from the second chiplet; and
at the protocol layer of the first chiplet, generating second data associated with the second protocol from the received first data based on the conversion information.
2 . The method according to claim 1 , wherein
the first chiplet further includes a bus system,
the receiving the first data includes receiving the first data through the bus system,
the first data includes the first protocol type transaction,
and
the second data includes a payload of a first die-to-die interface flit associated with the second protocol.
3 . The method according to claim 2 , wherein
the protocol layer includes a processor and a sub-memory, and
the generating the second data includes:
by the processor, determining an encoding rule based on the encoding information associated with the second protocol; and
by the processor, generating the payload of the first die-to-die interface flit by encoding the first protocol type transaction according to the determined encoding rule, wherein the first protocol type transaction is stored in the sub-memory.
4 . The method according to claim 2 , wherein
the first chiplet further includes an adapter layer, and
the method further includes:
by the adapter layer, generating a header of the first die-to-die interface flit associated with the second protocol; and
by the adapter layer, generating the first die-to-die interface flit by combining the header and the payload.
5 . The method according to claim 2 , wherein, if the second protocol associated with the second chiplet is a uni-directional protocol from the first chiplet to the second chiplet,
the conversion information includes only conversion information from the first chiplet to the second chiplet.
6 . The method according to claim 1 , wherein
the first chiplet further includes an adapter layer,
the receiving the first data includes receiving the first data from the adapter layer,
the first data includes a payload of a second die-to-die interface flit associated with the first protocol,
and
the second data includes the second protocol type transaction.
7 . The method according to claim 6 , wherein
the protocol layer includes a processor, and
the generating the second data includes:
by the processor, determining a decoding rule based on the decoding information associated with the first protocol; and
by the processor, generating the second protocol type transaction by decoding the payload of the second die-to-die interface flit according to the determined decoding rule.
8 . The method according to claim 6 , wherein the method further includes, by the adapter layer, extracting the payload from the second die-to-die interface flit.
9 . The method according to claim 1 , wherein
the conversion information includes encoding or decoding information associated with the second chiplet, and
the encoding or decoding information associated with the second chiplet includes information on one or more bus channels of the second chiplet, and information indicating a region and a size of bits allocated to each of the one or more bus channels.
10 . The method according to claim 9 , wherein the conversion information further includes an indicator code that indicates an operable bus channel of one or more bus channels of the second chiplet.
11 . A chiplet system, wherein
the chiplet system includes a first chiplet associated with a first protocol and a second chiplet associated with a second protocol, the chiplet system further including an interface between the first chiplet and the second chiplet,
the first chiplet includes a controller including a protocol layer, and
the protocol layer of the first chiplet is configured to:
receive first data associated with the first protocol;
receive conversion information including encoding information associated with the second protocol or decoding information associated with the first protocol from the second chiplet; and
generate, at the first chiplet, second data associated with the second protocol from the received first data based on the conversion information.
12 . The chiplet system of claim 11 , wherein
the first chiplet further includes a bus system,
the receiving the first data includes receiving the first data through the bus system,
the first data includes the first protocol type transaction,
and
the second data includes a payload of a first die-to-die interface flit associated with the second protocol.
13 . The chiplet system according to claim 12 , wherein
the protocol layer includes a processor and a sub-memory, and
the generating the second data includes:
by the processor, determining an encoding rule based on the encoding information associated with the second protocol; and
by the processor, generating the payload of the first die-to-die interface flit by encoding the first protocol type transaction according to the determined encoding rule,
wherein the first protocol type transaction is stored in the sub-memory.
14 . The chiplet system according to claim 12 , wherein
the first chiplet further includes an adapter layer, and
the adaptive layer is configured to:
generate a header of the first die-to-die interface flit associated with the second protocol; and
generate the first die-to-die interface flit by combining the header and the payload.
15 . The chiplet system according to claim 12 , wherein, if the second protocol associated with the second chiplet is a uni-directional protocol from the first chiplet to the second chiplet,
the conversion information includes only conversion information from the first chiplet to the second chiplet.
16 . The chiplet system according to claim 11 , wherein
the first chiplet further includes an adapter layer, and
the receiving the first data includes receiving the first data from the adapter layer,
the first data includes a payload of a second die-to-die interface flit associated with the first protocol,
and
the second data includes the second protocol type transaction.
17 . The chiplet system according to claim 16 , wherein
the protocol layer includes a processor, and
the generating the second data includes:
by the processor, determining a decoding rule based on the decoding information associated with the first protocol; and
by the processor, generating the second protocol type transaction by decoding the payload of the second die-to-die interface flit according to the determined decoding rule.
18 . The chiplet system according to claim 16 , wherein the adapter layer is configured to extract the payload from the second die-to-die interface flit.
19 . The chiplet system according to claim 11 , wherein
the conversion information includes encoding or decoding information associated with the second chiplet, and
the encoding or decoding information associated with the second chiplet includes information on one or more bus channels of the second chiplet, and information indicating a region and a size of bits allocated to each of the one or more channels.
20 . The chiplet system according to claim 19 , wherein the conversion information further includes an indicator code that indicates an operable bus channel of one or more bus channels of the second chiplet.