Frequency correction loop with deadzone and hysteresis

1 . A semiconductor device comprising:

a phase lock loop of a timing circuit, the phase lock loop comprising:

a voltage-controlled oscillator;

a sub-sampling phase lock loop circuit; and

a frequency correction loop circuit, the frequency correction loop circuit being configured to:

activate a charge pump to inject a charge into the voltage-controlled oscillator based on a phase difference between a reference signal and a feedback signal being greater in magnitude than a deadzone delay parameter plus a hysteresis delay parameter; and

de-activate the charge pump based on the magnitude of the phase difference between the reference signal and the feedback signal falling below the deadzone delay parameter, wherein the deadzone delay parameter and the hysteresis delay parameter are each separately programmable.

2 . The semiconductor device of claim 1 , wherein the frequency correction loop circuit comprises a phase detector, the phase detector comprising:

a first latch that is configured to be set based on the reference signal to generate a first latch output signal;

a second latch that is configured to be set based on the feedback signal to generate a second latch output signal;

a third latch that is configured to be set based on the first latch output signal, the deadzone delay parameter and the hysteresis delay parameter; and

a fourth latch that is configured to be set based on the second latch output signal, the deadzone delay parameter and the hysteresis delay parameter.

3 . The semiconductor device of claim 2 , wherein:

the first latch and the second latch are configured to be reset based on the first latch output signal and second latch output signal both being set;

the third latch is configured to be reset based on the first latch output signal of the first latch and the deadzone delay parameter; and

the fourth latch is configured to be reset based on the second latch output signal of the second latch and the deadzone delay parameter.

4 . The semiconductor device of claim 1 , wherein the sub-sampling phase lock loop circuit is configured to activate and de-activate the frequency correction loop circuit based on the reference signal and feedback from the voltage-controlled oscillator.

5 . The semiconductor device of claim 1 , wherein the deadzone delay parameter corresponds to one half of a period of the reference signal.

6 . A frequency correction loop of a timing circuit, the frequency correction loop comprising:

a charge pump that is configured to inject a charge into a voltage-controlled oscillator of the timing circuit; and

a phase detector that is configured to control an activation of the charge pump, the phase detector comprising:

a first latch that is configured to be set based on a reference signal to generate a first latch output signal;

a second latch that is configured to be set based on a feedback signal from the voltage-controlled oscillator to generate a second latch output signal;

a first latch delay circuit;

a third latch that is configured to be set based on the first latch output signal and a first delay signal output by the first latch delay circuit;

a second latch delay circuit; and

a fourth latch that is configured to be set based on the second latch output signal and a second delay signal output by the second latch delay circuit, wherein the first and second latch delay circuits are each configured with a modifiable delay parameter that is configured to adjust a delay between a setting of the corresponding first and second latches and a setting of the corresponding third and fourth latches, wherein:

the first latch delay circuit and the second latch delay circuit are each configured with a modifiable delay parameter, comprising a deadzone delay parameter and a hysteresis delay parameter, that is configured to adjust a delay between a setting of the corresponding first latch and second latch and a setting of the corresponding third latch and fourth latch; and

the deadzone delay parameter and the hysteresis delay parameter are each separately programmable.

7 . The frequency correction loop of claim 6 , wherein the deadzone delay parameter corresponds to one half of a period of the reference signal.

8 . The frequency correction loop of claim 6 , wherein the delay between the setting of the corresponding first latch and second latch latches and the setting of the corresponding third latch and fourth latch comprises a combination of the deadzone delay parameter and the hysteresis delay parameter.

9 . A semiconductor device comprising a phase detector of a timing circuit, the phase detector being configured to:

control an activation of a charge pump of the timing circuit, the charge pump being configured to inject a charge into a voltage-controlled oscillator of the timing circuit;

enter a set state from a reset state in response to a phase difference between a reference signal and a feedback signal exceeding a predetermined deadzone delay corresponding to the reference signal plus a predetermined hysteresis delay, the phase detector being configured to activate the charge pump when in the set state and disable the charge pump when in the reset state; and

enter the reset state from the set state in response to the phase difference between the reference signal and the feedback signal being reduced to less than the predetermined deadzone delay,

wherein the predetermined deadzone delay and the predetermined hysteresis delay are each separately programmable.

10 . The semiconductor device of claim 9 wherein the reset state of the phase detector corresponds to a source output and a sink output of the phase detector being low.

11 . The semiconductor device of claim 9 wherein the set state of the phase detector corresponds to one of a source output and a sink output of the phase detector being high.

12 . The semiconductor device of claim 9 wherein:

the phase detector comprises a first pair of latches and a second pair of latches;

the first pair of latches are set based on one of the reference signal and the feedback signal, respectively; and

the second pair of latches are each set in response to a corresponding one of the first pair of latches being set and the phase difference between the reference signal and the feedback signal exceeding the predetermined deadzone delay corresponding to the reference signal plus the predetermined hysteresis delay.

13 . The semiconductor device of claim 12 wherein the phase detector comprises a pair of latch delay circuits, each latch delay circuit being disposed between the reference signal or feedback signal and a corresponding one of the second pair of latches and defining the predetermined deadzone delay and the predetermined hysteresis delay.

14 . The semiconductor device of claim 9 wherein predetermined deadzone delay corresponds to half of a period of the reference signal.