Granted Patent B2

US 12,487,749 · App. 18/810,487 · Granted Dec 2, 2025

Inventor: Tsung-Chieh Yang (Hsinchu, TW)

Assignee: Silicon Motion, Inc.

G06F3/0613G06F3/0659G06F3/0679

Abstract

Claims (64)

1 . A flash memory controller, to be coupled between a host device and a flash memory module, comprising:

a specific buffer, for receiving and buffering specific data from the host device, the specific data to be stored into the flash memory module to form a super block, the super block being composed of a plurality of finger-shaped sub-blocks in a vertical direction and a plurality of wordlines in a horizontal direction; and

an error correction code circuit, coupled to the specific buffer, comprising:

a wordline-dimensional check code buffer, including a plurality of groups of wordline-dimensional sub-buffers, each group of wordline-dimensional sub-buffers including a plurality of sub-buffers; and

a finger-dimensional check code buffer, including a plurality of finger-dimensional sub-buffers;

wherein the error correction code circuit uses the wordline-dimensional check code buffer to perform a wordline-dimensional error correction code operation upon the specific data to generate wordline-dimensional check code data and uses the finger-dimensional check code buffer to perform a finger-dimensional error correction code operation upon an operation result of the wordline-dimensional error correction code operation with the specific data to generate finger-dimensional check code data; when a data error occurs in the super block, the wordline-dimensional check code data and the finger-dimensional check code data are used to correct the data error occurring in the super block to obtain the specific data.

2 . The flash memory controller of claim 1 , wherein the wordline-dimensional error correction code operation and the finger-dimensional error correction code operation are both implemented by using an exclusive-OR operation.

3 . The flash memory controller of claim 2 , wherein the error correction code circuit uses a first even-number sub-buffer in a first group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a first data of a first even-number finger sub-block of a specific wordline in the super block to generate and store a first portion of wordline-dimensional check code; and, the error correction code circuit uses a first odd-number sub-buffer in the first group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a second data, to be written into a first odd-number finger-shaped sub-block of the specific wordline, to generate and store a second portion of wordline-dimensional check code.

4 . The flash memory controller of claim 3 , wherein the error correction code circuit uses a second even-number sub-buffer in the first group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a third data, to be written into a second even-number finger-shaped sub-block of the specific wordline, to generate and store a third portion of wordline-dimensional check code, and then the error correction code circuit uses a first finger-dimensional sub-buffer of the finger-dimensional check code buffer to perform the exclusive-OR operation upon the first portion of wordline-dimensional check code and the third portion of wordline-dimensional check code to generate and store a first portion of finger-dimensional check code, the first portion of finger-dimensional check code being used to correct an error occurring in data of a plurality of even-number finger-shaped sub-blocks s in the specific wordline; and, the error correction code circuit uses a second odd-number sub-buffer in the first group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a fourth data, to be written into a second odd-number finger-shaped sub-block of the specific wordline, to generate and store a fourth portion of wordline-dimensional check code, and then the error correction code circuit uses a second finger-dimensional sub-buffer of the finger-dimensional check code buffer to perform the exclusive-OR operation upon the second portion of wordline-dimensional check code and the fourth portion of wordline-dimensional check code to generate and store a second portion of finger-dimensional check code, the second portion of finger-dimensional check code being used to correct an error occurring in data of a plurality of odd-number finger-shaped sub-blocks in the specific wordline.

5 . The flash memory controller of claim 4 , wherein for a next wordline corresponding to the specific wordline, the error correction code circuit uses a first even-number sub-buffer in a second group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a fifth data, to be written into a first even-number finger-shaped sub-block of the next wordline, to generate and store a fifth portion of wordline-dimensional check code, and then the error correction code circuit uses a first odd-number sub-buffer in the second group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a sixth data, to be written into a first odd-number finger-shaped sub-block of the next wordline, to generate and store a sixth portion of wordline-dimensional check code; the error correction code circuit uses a second even-number sub-buffer in the second group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a seventh data, to be written into a second even-number finger-dimensional sub-block of the next wordline, to generate and store a seventh portion of wordline-dimensional check code, and then the error correction code circuit uses the first finger-dimensional sub-buffer of the finger-dimensional check code buffer to perform the exclusive-OR operation upon the fifth part wordline-dimensional check code and the seventh portion of wordline-dimensional check code to generate and store a third portion of finger-dimensional check code, the third portion of finger-dimensional check code being used to correct an error occurring in data of a plurality of even-number finger-shaped sub-blocks in the next wordline; and, the error correction code circuit uses a second odd-number sub-buffer in the second group of wordline-dimensional sub-buffers to perform the exclusive operation upon an eighth data, to be written into a second odd-number finger-shaped sub-block of the next wordline, to generate and store an eighth portion of wordline-dimensional check code, and then the error correction code circuit uses the second finger-dimensional sub-buffer of the finger-dimensional check code buffer to perform the exclusive-OR operation upon the sixth portion of wordline-dimensional check code and the eighth portion of wordline-dimensional check code to generate and store a fourth portion of finger-dimensional check code, the fourth portion of finger-dimensional check code being used to correct an error occurring in data of a plurality of odd-number finger-shaped sub-blocks in the next wordline.

6 . The flash memory controller of claim 2 , wherein the error correction code circuit uses a first group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a first data, to written into a first even-number finger-shaped sub-block of a first wordline of the super block, to generate and store a first portion of wordline-dimensional check code; the error correction code circuit uses a second groups of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a second data, to be written into a first odd-number finger-shaped sub-block of the first wordline, to generate and store a second portion of wordline-dimensional check code; the error correction code circuit uses a third group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a third data, to be written into a second even-number finger-shaped sub-block of the first wordline to generate and store a third portion of wordline-dimensional check code; the error correction code circuit uses a fourth group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a fourth data, to be written into a second odd-number finger-shaped sub-block of the first wordline, to generate and store a fourth portion of wordline-dimensional check code.

7 . The flash memory controller of claim 6 , wherein the error correction code circuit respectively backs up, swaps, and temporarily stores the first portion of wordline-dimensional check code, the second portion of wordline-dimensional check code, the third portion of wordline-dimensional check code, and the fourth portion of wordline-dimensional check code from the first group of wordline-dimensional sub-buffers, the second group of wordline-dimensional sub-buffers, the third group of wordline-dimensional sub-buffers, and the fourth group of wordline-dimensional sub-buffers respectively into the specific buffer; the error correction code circuit then uses the first group of wordline-dimensional sub-buffers to perform the exclusive-Or operation upon the first portion of wordline-dimensional check code previously stored in the first group of wordline-dimensional sub-buffers and the third portion of wordline-dimensional check code obtain from the specific buffer to generate and store a first portion of finger-dimensional check code; the error correction code circuit then uses the second group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon the second portion of wordline-dimensional check code previously stored in the second group of wordline-dimensional sub-buffers and the fourth portion of wordline-dimensional check code obtained from the specific buffer to generate and store a second finger-dimensional check code; the first portion of finger-dimensional check code is used to correct an error occurring in data of a plurality of even-number finger-shaped sub-blocks within the first wordline, and the second portion of finger-dimensional check code is used to correct an error occurring in data of a plurality of odd-number finger-shaped sub-blocks within the first wordline.

8 . The flash memory controller of claim 7 , wherein a combination of the first portion of wordline-dimensional check code, the second portion of wordline-dimensional check code, the third portion of wordline-dimensional check code and the fourth portion of wordline-dimensional check code, stored in the specific buffer, is wordline-dimensional check code data corresponding to the first wordline; the error correction code circuit uses the first group of wordline-dimensional sub-buffers, the second group of wordline-dimensional sub-buffers, the third group of wordline-dimensional sub-buffers, and the fourth group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon data of a second wordline to generate and store wordline-dimensional check code data corresponding to the second wordline, and then the error correction code circuit backs up, swaps, and stores the wordline-dimensional check code data corresponding to the second wordline into the specific buffer; the error correction code circuit uses the first group of wordline-dimensional sub-buffers, the second group of wordline-dimensional sub-buffers, the third group of wordline-dimensional sub-buffers, and the fourth group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon data of a third wordline to generate and store wordline-dimensional check code data corresponding to the third wordline, and then backs up, swaps, and stores the wordline-dimensional check code data corresponding to the third wordline into the specific buffer; and, the error correction code circuit performs the exclusive-OR operation upon the wordline-dimensional check code data corresponding to the third wordline, respectively buffered in the first group of wordline-dimensional sub-buffers, the second group of wordline-dimensional sub-buffers, the third group of wordline-dimensional sub-buffers, and the fourth group of wordline-dimensional sub-buffers, and the wordline-dimensional check code data corresponding the first wordline, obtained from the specific buffer, to generate a merged wordline-dimensional check code data corresponding to the first wordline and the third wordline; the third wordline follows the second wordline which flows the first wordline.

9 . The flash memory controller of claim 8 , wherein the specific buffer only temporarily stores the data amount of wordline-dimensional check code data corresponding to three wordlines at most.

10 . An operating method of a flash memory controller, the flash memory controller to be coupled between a host device and a flash memory module, and the operating method comprises:

providing a specific buffer to receive and buffer specific data from the host device, the specific data to be stored into the flash memory module to form a super block, the super block being composed of a plurality of finger-shaped sub-blocks in a vertical direction and a plurality of wordlines in a horizontal direction;

providing an error correction code circuit comprising:

a wordline-dimensional check code buffer, including a plurality of groups of wordline-dimensional sub-buffers, each group of wordline-dimensional sub-buffers including a plurality of sub-buffers; and

a finger-dimensional check code buffer, including a plurality of finger-dimensional sub-buffers;

using the wordline-dimensional check code buffer to perform a wordline-dimensional error correction code operation upon the specific data to generate wordline-dimensional check code data and using the finger-dimensional check code buffer to perform a finger-dimensional error correction code operation upon an operation result of the wordline-dimensional error correction code operation with the specific data to generate finger-dimensional check code data; and

when a data error occurs in the super block, using the wordline-dimensional check code data and the finger-dimensional check code data to correct the data error occurring in the super block to obtain the specific data.

11 . The operating method of claim 10 , wherein the wordline-dimensional error correction code operation and the finger-dimensional error correction code operation are both implemented by using an exclusive-OR operation.

12 . The operating method of claim 11 , further comprising:

using a first even-number sub-buffer in a first group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a first data of a first even-number finger sub-block of a specific wordline in the super block to generate and store a first portion of wordline-dimensional check code; and

using a first odd-number sub-buffer in the first group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a second data, to be written into a first odd-number finger-shaped sub-block of the specific wordline, to generate and store a second portion of wordline-dimensional check code.

13 . The operating method of claim 12 , further comprising:

using a second even-number sub-buffer in the first group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a third data, to be written into a second even-number finger-shaped sub-block of the specific wordline, to generate and store a third portion of wordline-dimensional check code;

using a first finger-dimensional sub-buffer of the finger-dimensional check code buffer to perform the exclusive-OR operation upon the first portion of wordline-dimensional check code and the third portion of wordline-dimensional check code to generate and store a first portion of finger-dimensional check code, the first portion of finger-dimensional check code being used to correct an error occurring in data of a plurality of even-number finger-shaped sub-blocks s in the specific wordline;

using a second odd-number sub-buffer in the first group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a fourth data, to be written into a second odd-number finger-shaped sub-block of the specific wordline, to generate and store a fourth portion of wordline-dimensional check code; and

using a second finger-dimensional sub-buffer of the finger-dimensional check code buffer to perform the exclusive-OR operation upon the second portion of wordline-dimensional check code and the fourth portion of wordline-dimensional check code to generate and store a second portion of finger-dimensional check code, the second portion of finger-dimensional check code being used to correct an error occurring in data of a plurality of odd-number finger-shaped sub-blocks in the specific wordline.

14 . The operating method of claim 13 , wherein for a next wordline corresponding to the specific wordline, the operating method further comprising:

using a first even-number sub-buffer in a second group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a fifth data, to be written into a first even-number finger-shaped sub-block of the next wordline, to generate and store a fifth portion of wordline-dimensional check code;

using a first odd-number sub-buffer in the second group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a sixth data, to be written into a first odd-number finger-shaped sub-block of the next wordline, to generate and store a sixth portion of wordline-dimensional check code;

using a second even-number sub-buffer in the second group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a seventh data, to be written into a second even-number finger-dimensional sub-block of the next wordline, to generate and store a seventh portion of wordline-dimensional check code;

using the first finger-dimensional sub-buffer of the finger-dimensional check code buffer to perform the exclusive-OR operation upon the fifth part wordline-dimensional check code and the seventh portion of wordline-dimensional check code to generate and store a third portion of finger-dimensional check code, the third portion of finger-dimensional check code being used to correct an error occurring in data of a plurality of even-number finger-shaped sub-blocks in the next wordline;

using a second odd-number sub-buffer in the second group of wordline-dimensional sub-buffers to perform the exclusive operation upon an eighth data, to be written into a second odd-number finger-shaped sub-block of the next wordline, to generate and store an eighth portion of wordline-dimensional check code; and

using the second finger-dimensional sub-buffer of the finger-dimensional check code buffer to perform the exclusive-OR operation upon the sixth portion of wordline-dimensional check code and the eighth portion of wordline-dimensional check code to generate and store a fourth portion of finger-dimensional check code, the fourth portion of finger-dimensional check code being used to correct an error occurring in data of a plurality of odd-number finger-shaped sub-blocks in the next wordline.

15 . The operating method of claim 11 , further comprising:

using a first group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a first data, to written into a first even-number finger-shaped sub-block of a first wordline of the super block, to generate and store a first portion of wordline-dimensional check code;

using a second groups of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a second data, to be written into a first odd-number finger-shaped sub-block of the first wordline, to generate and store a second portion of wordline-dimensional check code;

using a third group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a third data, to be written into a second even-number finger-shaped sub-block of the first wordline to generate and store a third portion of wordline-dimensional check code; and

using a fourth group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon a fourth data, to be written into a second odd-number finger-shaped sub-block of the first wordline, to generate and store a fourth portion of wordline-dimensional check code.

16 . The operating method of claim 15 , further comprising:

respectively backing up, swapping, and temporarily storing the first portion of wordline-dimensional check code, the second portion of wordline-dimensional check code, the third portion of wordline-dimensional check code, and the fourth portion of wordline-dimensional check code from the first group of wordline-dimensional sub-buffers, the second group of wordline-dimensional sub-buffers, the third group of wordline-dimensional sub-buffers, and the fourth group of wordline-dimensional sub-buffers respectively into the specific buffer;

using the first group of wordline-dimensional sub-buffers to perform the exclusive-Or operation upon the first portion of wordline-dimensional check code previously stored in the first group of wordline-dimensional sub-buffers and the third portion of wordline-dimensional check code obtain from the specific buffer to generate and store a first portion of finger-dimensional check code; and

using the second group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon the second portion of wordline-dimensional check code previously stored in the second group of wordline-dimensional sub-buffers and the fourth portion of wordline-dimensional check code obtained from the specific buffer to generate and store a second finger-dimensional check code;

wherein the first portion of finger-dimensional check code is used to correct an error occurring in data of a plurality of even-number finger-shaped sub-blocks within the first wordline, and the second portion of finger-dimensional check code is used to correct an error occurring in data of a plurality of odd-number finger-shaped sub-blocks within the first wordline.

17 . The operating method of claim 16 , wherein a combination of the first portion of wordline-dimensional check code, the second portion of wordline-dimensional check code, the third portion of wordline-dimensional check code and the fourth portion of wordline-dimensional check code, stored in the specific buffer, is wordline-dimensional check code data corresponding to the first wordline, and the operation further comprises:

using the first group of wordline-dimensional sub-buffers, the second group of wordline-dimensional sub-buffers, the third group of wordline-dimensional sub-buffers, and the fourth group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon data of a second wordline to generate and store wordline-dimensional check code data corresponding to the second wordline;

backing up, swapping, and storing the wordline-dimensional check code data corresponding to the second wordline into the specific buffer;

using the first group of wordline-dimensional sub-buffers, the second group of wordline-dimensional sub-buffers, the third group of wordline-dimensional sub-buffers, and the fourth group of wordline-dimensional sub-buffers to perform the exclusive-OR operation upon data of a third wordline to generate and store wordline-dimensional check code data corresponding to the third wordline;

backing up, swapping, and storing the wordline-dimensional check code data corresponding to the third wordline into the specific buffer; and

performing the exclusive-OR operation upon the wordline-dimensional check code data corresponding to the third wordline, respectively buffered in the first group of wordline-dimensional sub-buffers, the second group of wordline-dimensional sub-buffers, the third group of wordline-dimensional sub-buffers, and the fourth group of wordline-dimensional sub-buffers, and the wordline-dimensional check code data corresponding the first wordline, obtained from the specific buffer, to generate a merged wordline-dimensional check code data corresponding to the first wordline and the third wordline;

wherein the third wordline follows the second wordline which flows the first wordline.

18 . The operating method of claim 17 , wherein the specific buffer only temporarily stores the data amount of wordline-dimensional check code data corresponding to three wordlines at most.

19 . A storage device, comprising:

a flash memory module, including a plurality of channels, each channel including a plurality of flash memory chips, each flash memory chip including a plurality of blocks on a plurality of planes; and

a flash memory controller, to be coupled to the flash memory module, comprising:

a specific buffer, for receiving and buffering specific data from a host device, the specific data to be stored into the flash memory module to form a super block, the super block being composed of a plurality of finger-shaped sub-blocks in a vertical direction and a plurality of wordlines in a horizontal direction; and

an error correction code circuit, coupled to the specific buffer, comprising:

a wordline-dimensional check code buffer, including a plurality of groups of wordline-dimensional sub-buffers, each group of wordline-dimensional sub-buffers including a plurality of sub-buffers; and

a finger-dimensional check code buffer, including a plurality of finger-dimensional sub-buffers;

wherein the error correction code circuit uses the wordline-dimensional check code buffer to perform a wordline-dimensional error correction code operation upon the specific data to generate wordline-dimensional check code data and uses the finger-dimensional check code buffer to perform a finger-dimensional error correction code operation upon an operation result of the wordline-dimensional error correction code operation with the specific data to generate finger-dimensional check code data; when a data error occurs in the super block, the wordline-dimensional check code data and the finger-dimensional check code data are used to correct the data error occurring in the super block to obtain the specific data.

20 . The storage device of claim 19 , wherein the wordline-dimensional error correction code operation and the finger-dimensional error correction code operation are both implemented by using an exclusive-OR operation.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (17)