IP Library Granted Patent US 12,608,288
Granted Patent B1
US 12,608,288 · App. 18/816,071 · Granted Apr 21, 2026

Fault state recovery using predefined configurations

Inventors: John Hayes (Mountain View, CA); Volkmar Uhlig (Cupertino, CA); Richard A. Swetz (Los Altos, CA); Daniel P. Potts (Sydney, AU)
Assignee: Applied Intuition, Inc.
G06F11/1658G06F11/0739G06F11/2028G06F11/2041G07C5/0808G06F2201/805
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Quick Facts
Patent No.
US 12,608,288
App. No.
18/816,071
Granted
Apr 21, 2026
Kind
B1
Abstract

Fault state recovery using predefined configurations, including: determining that a first node of a plurality of nodes has failed; identifying, based on the first node failing, a failure state from a plurality of predefined failure states each corresponding to a different combination of one or more failed nodes, wherein each of the plurality of predefined failure states corresponds to a respective configuration of a plurality of configurations; and applying the respective configuration corresponding to the identified failure state, wherein applying the respective configuration comprises at least one of: updating one or more memory mapping tables based on the respective configuration or copying data from memory locations used based on a previous configuration to memory locations indicated in the respective configuration.

Claims (44)

1 . A method comprising:

determining that a first node of a plurality of nodes has failed;

identifying, based on the first node failing, a failure state from a plurality of predefined failure states each corresponding to a different combination of one or more failed nodes;

applying the respective configuration corresponding to the identified failure state, by at least one of updating one or more memory mapping tables based on the respective configuration or copying data from memory locations used based on a previous configuration to memory locations indicated in the respective configuration; and

determining, during a code compilation, the plurality of predefined failure states.

2 . The method of claim 1 , further comprising determining the failure state by identifying, from a plurality of predefined states, a current state and identifying a transition to the failure state based on a failing node.

3 . The method of claim 1 , further comprising determining, during the code compilation, the plurality of configurations.

4 . The method of claim 1 , further comprising:

determining that the first node is operational;

determining, based on the failure state and in response to determining that the first node is operational, a current state;

determining, based on the current state, another configuration; and

applying the other configuration.

5 . The method of claim 1 , further comprising updating one or more functional assignments for the plurality of nodes based on the respective configuration.

6 . The method of claim 1 , wherein determining that the first node has failed comprises receiving, by an exception handler, an exception generated by the first node.

7 . The method of claim 1 , wherein determining that the first node has failed comprises determining that the first node has written invalid data to a memory address accessible by another node.

8 . The method of claim 1 , wherein determining that the first node has failed comprises determining that the first node has failed to write data within a time window to a memory address for access by another node.

9 . An apparatus comprising one or more processors and memory storing instructions that, when executed, cause the one or more processors to perform steps comprising:

determining that a first node of a plurality of nodes has failed;

identifying, based on the first node failing, a failure state from a plurality of predefined failure states each corresponding to a different combination of one or more failed nodes;

applying the respective configuration corresponding to the identified failure state, by at least one of updating one or more memory mapping tables based on the respective configuration or copying data from memory locations used based on a previous configuration to memory locations indicated in the respective configuration; and

determining, during a code compilation, the plurality of predefined failure states.

10 . The apparatus of claim 9 , further comprising determining the failure state by identifying, from a plurality of predefined states, a current state and identifying a transition to the failure state based on a failing node, wherein the steps further comprise determining, during a code compilation, the plurality of predefined failure states.

11 . The apparatus of claim 9 , wherein the steps further comprise determining, during the code compilation, the plurality of configurations.

12 . The apparatus of claim 9 , wherein the steps further comprise:

determining that the first node is operational;

determining, based on the failure state and in response to determining that the first node is operational, a current state;

determining, based on the current state, another configuration; and

applying the other configuration.

13 . The apparatus of claim 9 , wherein the steps further comprise updating one or more functional assignments for the plurality of nodes based on the respective configuration.

14 . The apparatus of claim 9 , wherein determining that the first node has failed comprises receiving, by an exception handler, an exception generated by the first node.

15 . The apparatus of claim 9 , wherein determining that the first node has failed comprises determining that the first node has written invalid data to a memory address accessible by another node.

16 . The apparatus of claim 9 , wherein determining that the first node has failed comprises determining that the first node has failed to write data within a time window to a memory address for access by another node.

17 . A computer program product comprising a non-transitory computer readable medium and computer program instructions disposed upon the non-transitory computer readable medium, the computer program instructions that, when executed, cause a computer system of an autonomous vehicle to carry out the steps of:

determining that a first node of a plurality of nodes has failed;

identifying, based on the first node failing, a failure state from a plurality of predefined failure states each corresponding to a different combination of one or more failed nodes;

applying the respective configuration corresponding to the identified failure state, by at least one of updating one or more memory mapping tables based on the respective configuration or copying data from memory locations used based on a previous configuration to memory locations indicated in the respective configuration; and

determining, during a code compilation, the plurality of predefined failure states.

18 . The computer program product of claim 17 , further comprising determining the failure state by identifying, from a plurality of predefined states, a current state and identifying a transition to the failure state based on a failing node.

19 . The computer program product of claim 17 , wherein the steps further comprise determining, during the code compilation, the plurality of configurations.

20 . The computer program product of claim 17 , wherein the steps further comprise:

determining that the first node is operational;

determining, based on the failure state and in response to determining that the first node is operational, a current state;

determining, based on the current state, another configuration; and

applying the other configuration.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2024
From: HAYES, JOHN; UHLIG, VOLKMAR; SWETZ, RICHARD A.; POTTS, DANIEL P.
To: GHOST AUTONOMY INC.
Reel/Frame 068410/0352 →
Continuity (3)
Continuation 18295305 · Apr 4, 2023
Continuation 17083773 · Oct 29, 2020
Provisional Application 62927918 · Oct 30, 2019
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