Memory device and power-on reading method thereof
A power-on reading method of a memory device includes: generating a power-on signal according to a voltage level of a power voltage of the memory device; respectively detecting a plurality of ready states of a plurality of circuits in the memory device sequentially to generate a plurality of ready signals; reading a plurality of fuse states sequentially to generate a plurality of fuse state signals; and shifting a reference signal sequentially to generate a read pass indication signal according to the power-on signal, the plurality of ready signals and the plurality of fuse state signals by a plurality of registers coupled in series, wherein each of the plurality of registers is triggered when the power-on signal, corresponding ready signal or corresponding fuse state signal is at a setting logic value.
1 . A power-on reading method of a memory device, comprising:
generating a power-on signal according to a voltage level of a power voltage of the memory device;
respectively detecting a plurality of ready states of a plurality of circuits in the memory device sequentially to generate a plurality of ready signals;
reading a plurality of fuse states sequentially to generate a plurality of fuse state signals; and
shifting a reference signal sequentially to generate a read pass indication signal according to the power-on signal, the plurality of ready signals and the plurality of fuse state signals by a plurality of shift registers coupled in series,
wherein each of the plurality of shift registers is triggered when the power-on signal, corresponding ready signal or corresponding fuse state signal is at a setting logic value.
2 . The power-on reading method according to claim 1 , further comprising:
storing output signals of the plurality of shift registers and the read pass indication signal to a storage component.
3 . The power-on reading method according to claim 2 , further comprising:
outputting stored data for reporting a plurality event states by the storage component.
4 . The power-on reading method according to claim 1 , wherein the plurality of ready states of the plurality of circuits comprises a band gap reference voltage ready signal, a charge pump ready signal and a high power voltage settling time elapsed signal.
5 . The power-on reading method according to claim 4 , wherein a step of respectively detecting the plurality of ready states of the plurality of circuits in the memory device sequentially comprises:
detecting the band gap reference voltage ready signal, the charge pump ready signal and the high power voltage settling time elapsed signal in sequential.
6 . The power-on reading method according to claim 1 , further comprising:
corresponding to each of the shift registers, performing a logic operation on an output signal of previous stage shift register with corresponding ready signal or corresponding fuse state signal to generate a trigger signal; and
providing the trigger signal to a clock end of current stage shift register.
7 . The power-on reading method according to claim 6 , wherein the logic operation is an AND operation.
8 . A memory device, comprising:
a controller, being configured to:
generate a power-on signal according to a voltage level of a power voltage of the memory device;
respectively detect a plurality of ready states of a plurality of circuits in the memory device sequentially to generate a plurality of ready signals; and
read a plurality of fuse states sequentially to generate a plurality of fuse state signals; and
a shift register circuit, coupled to the controller, the shift register circuit being configured to shift a reference signal sequentially to generate a read pass indication signal according to the power-on signal, the plurality of ready signals and the plurality of fuse state signals by a plurality of shift registers coupled in series,
wherein each of a plurality of shift registers of the shift register circuit is triggered when the power-on signal, corresponding ready signal or corresponding fuse state signal is at a setting logic value.
9 . The memory device according to claim 8 , wherein the shift register circuit comprises:
the plurality of shift registers, coupled in series; and
a plurality of logic circuits, wherein each of the plurality of logic circuits is coupled to an output end of each of the plurality of shift registers.
10 . The memory device according to claim 8 , wherein a first stage shift register receives the power-on signal as a trigger signal, and the other stage shift resisters respectively receive the output signals of the plurality of logic circuits as trigger signals.
11 . The memory device according to claim 8 , further comprising:
a storage component, coupled to the shift register circuit, the storage component in configured to store output signals of the shift registers and the read pass indication signal.
12 . The memory device according to claim 11 , wherein the storage component further outputs stored data for reporting a plurality of event states of the memory device.
13 . The memory device according to claim 8 , wherein the plurality of ready states of the plurality of circuits comprises a band gap reference voltage ready signal, a charge pump ready signal and a high power voltage settling time elapsed signal.
14 . The memory device according to claim 8 , wherein the controller detects the band gap reference voltage ready signal, the charge pump ready signal and the high power voltage settling time elapsed signal in sequential.
15 . The memory device according to claim 8 , wherein each of the plurality of logic circuits performs a logic operation on an output signal of previous stage shift register with corresponding ready signal or corresponding fuse state signal to generate a trigger signal.
16 . The memory device according to claim 8 , wherein each of the plurality of logic circuits is an AND gate.