IP Library Patent Application 18825392
Patent Application
App. No. 18/825,392

SCALABLE COMMAND QUEUEING APPARATUSES AND METHODS

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Quick Facts
Patent No.
US None
App. No.
18/825,392
Abstract

A computing apparatus includes: a set of processing elements configured to execute an active command obtained from a plurality of commands; a first command queue; a second command queue; a bank controller configured to place respective subsets of the plurality of commands into the first and second command queues; and an array controller configured to: (i) select one of the first command queue and the second command queue, (ii) retrieve the active command from the selected one of the first command queue and the second command queue, and (iii) deploy the active command to each of the set of processing elements for execution.

Claims (65)

1 . A computing apparatus, comprising:

a set of processing elements configured to execute an active command obtained from a plurality of commands;

a first command queue;

a second command queue;

a bank controller configured to place respective subsets of the plurality of commands into the first and second command queues; and

an array controller configured to:

(i) select one of the first command queue and the second command queue,

(ii) retrieve the active command from the selected one of the first command queue and the second command queue, and

(iii) deploy the active command to each of the set of processing elements for execution.

2 . The computing apparatus of claim 1 , further comprising:

a further set of processing elements;

a third command queue and a fourth command queue configured to receive further respective subsets of the plurality of commands from the bank controller; and

a further array controller configured to:

(i) select one of the third command queue and the fourth command queue,

(ii) retrieve a further active command from the selected one of the third command queue and the fourth command queue, and

(iii) deploy the further active command to each of the further set of processing elements for execution.

3 . The computing apparatus of claim 1 , wherein the array controller is configured to select one of the first command queue and the second command queue by:

obtaining state information corresponding to execution resources associated with the set of processing elements;

obtaining a first candidate active command from the first command queue, and a second candidate active command from the second command queue; and

comparing the state information with the first and second candidate active commands.

4 . The computing apparatus of claim 3 , wherein the array controller is further configured to:

update the state information in response to deploying the active command to the processing elements.

5 . The computing apparatus of claim 3 , wherein the array controller is further configured to:

determine, based on the comparison, that execution of the first candidate active command is obstructed; and

select the second command queue.

6 . The computing apparatus of claim 3 , wherein the array controller is further configured to:

determine, based on the comparison, that execution of the first candidate active command and execution of the second candidate active command are each unobstructed; and

select one of the first and second command queues according to a configurable setting.

7 . The computing apparatus of claim 6 , wherein the configurable setting corresponds to one of (i) a run-to-empty command selection configuration, or (ii) a round-robin command selection configuration.

8 . The computing apparatus of claim 1 , wherein the subsets of the commands are associated with respective processing thread identifiers; and wherein the bank controller is configured to:

place commands associated with a first processing thread identifier in the first command queue; and

place commands associated with a second processing thread identifier in the second command queue.

9 . The computing apparatus of claim 1 , wherein the bank controller is configured to receive, from first command queue and the second command queue, respective capacity indicators defining whether the command queues can store further commands.

10 . A method in a computing apparatus, the method comprising:

at a bank controller of the computing apparatus, placing respective subsets of a plurality of commands into a first command queue and a second command queue of the computing apparatus;

at an array controller of the computing apparatus:

(i) selecting one of the first command queue and the second command queue,

(ii) retrieving an active command among the plurality of commands from the selected one of the first command queue and the second command queue, and

(iii) deploying the active command to each of a set of processing elements of the computing apparatus for execution; and

at the set of processing elements, executing the active command.

11 . The method of claim 10 , further comprising:

at the bank controller, placing further respective subsets of the plurality of commands into a third command queue and a fourth command queue;

at a further array controller of the computing apparatus:

(i) selecting one of the third command queue and the fourth command queue,

(ii) retrieving a further active command from the selected one of the third command queue and the fourth command queue, and

(iii) deploying the further active command to each of a further set of processing elements for execution; and

at the further set of processing elements, executing the further active command.

12 . The method of claim 10 , wherein selecting one of the first command queue and the second command queue includes:

obtaining state information corresponding to execution resources associated with the set of processing elements;

obtaining a first candidate active command from the first command queue, and a second candidate active command from the second command queue; and

comparing the state information with the first and second candidate active commands.

13 . The method of claim 12 , further comprising, at the array controller:

updating the state information in response to deploying the active command to the processing elements.

14 . The method of claim 12 , further comprising, at the array controller:

determining, based on the comparison, that execution of the first candidate active command is obstructed; and

selecting the second command queue.

15 . The method of claim 12 , further comprising, at the array controller:

determining, based on the comparison, that execution of the first candidate active command and execution of the second candidate active command are each unobstructed; and

selecting one of the first and second command queues according to a configurable setting.

16 . The method of claim 15 , wherein the configurable setting corresponds to one of (i) a run-to-empty command selection configuration, or (ii) a round-robin command selection configuration.

17 . The method of claim 10 , wherein the subsets of the commands are associated with respective processing thread identifiers; the method further comprising, at the bank controller:

placing commands associated with a first processing thread identifier in the first command queue; and

placing commands associated with a second processing thread identifier in the second command queue.

18 . The method of claim 10 , further comprising, at the bank controller:

receiving, from first command queue and the second command queue, respective capacity indicators defining whether the command queues can store further commands.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2026
From: UNTETHER AI CORPORATION
To: AT-MEMORY COMPUTING LP
Reel/Frame 075495/0905 →
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2025
From: NATIONAL BANK OF CANADA
To: UNTETHER AI CORPORATION
Reel/Frame 071655/0897 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2024
From: GRIESDORF, DUSTIN T.
To: UNTETHER AI CORPORATION
Reel/Frame 068497/0757 →