SILICON WAFERS HAVING PASSIVATED CONTACTS

1 . A wafer comprising:

a silicon core comprising a textured surface; and

a dielectric layer comprising a first thickness, wherein:

the textured surface comprises a plurality of features where each feature is characterized by a first point and a second point separated by a distance, H,

at least a portion of the features further comprise a solid channel positioned substantially at or near the first point, and

the solid channel passes through at least a portion of the first thickness.

2 . The wafer of claim 1 , further comprising a silicon layer comprising a second thickness, wherein:

the dielectric layer is positioned between the silicon core and the silicon layer,

the silicon layer maintains the textured shape of the textured silicon core, and

the solid channel passes through at least one of a portion of the first thickness or a portion of the second thickness or a combination thereof.

3 . The wafer of claim 2 , wherein the solid channel passes completely through each of the first thickness and the second thickness.

4 . The wafer of claim 1 , wherein the dielectric layer comprises at least one of a silicon oxide, an aluminum oxide, or a silicon nitride, or a combination thereof.

5 . The wafer of claim 1 , wherein H is between 100 nm and 10 μm.

6 . The wafer of claim 1 , wherein the feature comprises at least one of a pyramid, a cone, a ridge, a circular bulge, an inverted pyramid, an inverted cone, a dimple, or a combination thereof.

7 . The wafer of claim 6 , wherein the pyramid is characterized by:

a tip positioned at the first point,

a trough positioned at the second point,

at least three facets that meet to form the tip, and

the solid channel is positioned substantially at or near the tip.

8 . The wafer of claim 1 , wherein the silicon core comprises at least one of a crystalline silicon or a multi-crystalline silicon or a combination thereof.

9 . The wafer of claim 1 , wherein the first thickness is between 1.0 nm and 20 nm.

10 . The wafer of claim 1 , wherein the second thickness is between 5 nm and 300 nm.

11 . The wafer of claim 1 , wherein the solid channel has a diameter of less than 1000 nm

12 . The wafer of claim 1 , further comprising a concentration of solid channels between 1×10 4 solid channels/cm 2 and 1×10 10 solid channels/cm 2 .

13 . The wafer of claim 2 , further comprising a metal grid, wherein the silicon layer is positioned between the metal grid and the dielectric layer.

14 . The wafer of claim 13 , wherein the solid channel is positioned under the metal grid.

15 . The wafer of claim 2 , further comprising a sheet resistance, R s , between 576Ω/□ and 719 Ω/□.

16 . The wafer of claim 2 , further comprising an implied open-circuit voltage, iVoc, between 672 mV and 716 mV.

17 . A method comprising:

irradiating a wafer with a light, wherein:

the wafer comprises:

a silicon core comprising a textured surface;

a dielectric layer comprising a first thickness; and

a silicon layer comprising a second thickness, wherein;

the dielectric layer is positioned between the silicon core and the silicon layer;

the textured surface comprises a plurality of features where each feature is characterized by a first point and a second point separated by a distance, H, and the silicon layer maintains the textured shape of the textured silicon core; and

the irradiating creates a solid channel having a first diameter at the first point of at least a portion of the features.

18 . The method of claim 17 , further comprising, after the irradiating, an etching of the wafer, wherein the etching increases a diameter of a solid channel.

19 . The method of claim 17 , further comprising, before the irradiating, a pre-irradiating of the wafer with a second light, wherein in the pre-irradiating selectively weakens or thins the dielectric layer.