METHOD AND SYSTEM OF JUNCTION TERMINATION EXTENSION IN HIGH VOLTAGE SEMICONDUCTOR DEVICES

1 . A method for manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate comprising a first side and second side, wherein the semiconductor substrate is characterized by a first conductivity type;

epitaxially growing a first III-nitride semiconductor layer coupled to the first side of the semiconductor substrate, wherein the first III-nitride semiconductor layer is characterized by the first conductivity type;

epitaxially growing a second III-nitride semiconductor layer coupled to the first III-nitride semiconductor layer, wherein the second III-nitride semiconductor layer is characterized by a second conductivity type opposite the first conductivity type, and wherein the second III-nitride semiconductor layer comprises a contact region and a terminal region surrounding the contact region;

forming a mask layer on the second III-nitride semiconductor layer, wherein the mask layer is patterned with a planar region aligned with the contact region and a tapered region aligned with the terminal region of the second III-nitride semiconductor layer;

implanting ions into the terminal region of the second III-nitride semiconductor layer using the mask layer to form a tapered junction termination element in the terminal region of the second III-nitride semiconductor layer;

removing the mask layer; and

forming a contact structure in the contact region of the second III-nitride semiconductor layer.

2 . The method of claim 1 , further comprising forming a metallic field plate electrically coupled to the tapered junction termination element.

3 . The method of claim 1 , further comprising forming a metallic layer coupled to the second side of the semiconductor substrate.

4 . The method of claim 1 , wherein implanting the ions into the terminal region of the second III-nitride semiconductor layer comprises performing a multiple-energy ion implantation process.

5 . The method of claim 1 , wherein implanting the ions into the terminal region of the second III-nitride semiconductor layer comprises implanting the ions in a first region of the first III-nitride semiconductor layer that is at least partially aligned with the terminal region of the second III-nitride semiconductor layer.

6 . The method of claim 1 , wherein forming the contact structure in the contact region of the second III-nitride semiconductor layer comprises:

regrowing a third III-nitride semiconductor layer coupled to the contact region of the second III-nitride semiconductor layer, wherein the third III-nitride semiconductor layer is characterized by the second conductivity type; and

forming a metallic structure electrically coupled to the third III-nitride semiconductor layer.

7 . The method of claim 6 , wherein the third III-nitride semiconductor layer partially overlaps the tapered junction termination element.

8 . The method of claim 6 , wherein a dopant concentration of the third III-nitride semiconductor layer is greater than a dopant concentration of the second III-nitride semiconductor layer.

9 . The method of claim 1 , wherein forming the contact structure in the contact region of the second III-nitride semiconductor layer comprises:

etching at least a portion of the contact region of the second III-nitride semiconductor layer to form a recess in the contact region of the second III-nitride semiconductor layer; and

forming a metallic structure in the recess, wherein the metallic structure is electrically coupled to the second III-nitride semiconductor layer.

10 . The method of claim 1 , wherein:

providing the semiconductor substrate comprises providing the semiconductor substrate characterized by a first n-type dopant concentration; and

providing the second III-nitride semiconductor layer comprises providing the second III-nitride semiconductor layer characterized by a second n-type dopant concentration less than the first n-type dopant concentration.

11 . A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate comprising a first side and second side, wherein the semiconductor substrate is characterized by a first conductivity type;

providing a first III-nitride epitaxial semiconductor layer on the first side of the semiconductor substrate, wherein the first III-nitride epitaxial semiconductor layer is characterized by a varying dopant concentration of the first conductivity type;

providing a second III-nitride epitaxial semiconductor layer on the first III-nitride epitaxial semiconductor layer, wherein the second III-nitride epitaxial semiconductor layer is characterized by the first conductivity type and an upper surface, wherein the second III-nitride epitaxial semiconductor layer comprises a contact region including a contact structure comprising a plurality of source contacts, each of the plurality of source contacts formed on a portion of the upper surface of the second III-nitride epitaxial semiconductor layer;

providing a plurality of fins in the second III-nitride epitaxial semiconductor layer and a portion of the first III-nitride epitaxial semiconductor layer, wherein bottom surfaces of each of the plurality of fins extend from the first III-nitride epitaxial semiconductor layer and each of the plurality of fins is separated from an adjacent fin of the plurality of fins by a trench;

providing a third III-nitride epitaxial semiconductor layer epitaxially regrown in the trench separating the plurality of fins and defined by an upper surface coplanar with the upper surface of the second III-nitride epitaxial semiconductor layer, wherein:

the third III-nitride epitaxial semiconductor layer comprises a terminal region surrounding the contact region; and

the third III-nitride epitaxial semiconductor layer is characterized by a second conductivity type opposite to the first conductivity type;

providing a mask layer patterned with a planar region aligned with the contact region and a tapered region aligned with the terminal region;

ion implanting a dopant into the terminal region, wherein the tapered region of the mask layer provides a tapered junction termination element in the termination region comprising a linear profile and a non-conducting ion implanted zone in the termination region adjacent to the tapered junction termination element, wherein the non-conducting ion implanted zone is characterized by the linear profile; and

providing a gate conductive layer on the upper surface of the third III-nitride epitaxial semiconductor layer.

12 . The method of claim 11 , further comprising:

forming a metallic field plate electrically coupled to the tapered junction termination element.

13 . The method of claim 11 , wherein providing the gate conductive layer comprises:

providing a fourth III-nitride epitaxial semiconductor layer coupled to the contact region of the second III-nitride epitaxial semiconductor layer, wherein the fourth III-nitride epitaxial semiconductor layer is characterized by the first conductivity type; and

providing a metallic structure electrically coupled to the fourth III-nitride epitaxial semiconductor layer.

14 . A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate comprising a first side and second side, wherein the semiconductor substrate is characterized by a first conductivity type;

providing a first III-nitride epitaxial semiconductor layer on the first side of the semiconductor substrate, wherein the first III-nitride epitaxial semiconductor layer is characterized by a varying dopant concentration of the first conductivity type;

providing a second III-nitride epitaxial semiconductor layer on the first III-nitride epitaxial semiconductor layer, wherein the second III-nitride epitaxial semiconductor layer is characterized by the first conductivity type and an upper surface, wherein the second III-nitride epitaxial semiconductor layer comprises a contact region including a contact structure comprising a plurality of source contacts, each of the plurality of source contacts formed on a portion of the upper surface of the second III-nitride epitaxial semiconductor layer;

providing a plurality of fins in the second III-nitride epitaxial semiconductor layer and a portion of the first III-nitride epitaxial semiconductor layer, wherein bottom surfaces of each of the plurality of fins extend from the first III-nitride epitaxial semiconductor layer and each of the plurality of fins is separated from an adjacent fin of the plurality of fins by a trench;

providing a third III-nitride epitaxial semiconductor layer epitaxially regrown in the trenches separating the plurality of fins and defined by an upper surface coplanar with the upper surface of the second III-nitride epitaxial semiconductor layer and including a terminal region surrounding the contact region, wherein:

the terminal region comprises a tapered junction termination element having a linear profile and a non-conducting ion implanted zone adjacent to the tapered junction termination element;

the non-conducting ion implanted zone is characterized by the linear profile; and

the third III-nitride epitaxial semiconductor layer is characterized by a second conductivity type opposite to the first conductivity type; and

providing a gate conductive layer on the upper surface of the third III-nitride epitaxial semiconductor layer.

15 . The method of claim 14 , further comprising:

providing a conductive field plate electrically coupled to the tapered junction termination element.

16 . The method of claim 14 , wherein providing the gate conductive layer comprises:

providing a fourth III-nitride epitaxial semiconductor layer coupled to the contact region of the second III-nitride epitaxial semiconductor layer, wherein the fourth III-nitride epitaxial semiconductor layer is characterized by the first conductivity type; and

providing a metallic structure electrically coupled to the fourth III-nitride epitaxial semiconductor layer.

17 . The method of claim 14 , wherein:

providing the second III-nitride epitaxial semiconductor layer comprises providing the contact region of the second III-nitride epitaxial semiconductor layer comprising a recess; and

providing a metallic structure electrically coupled to the second III-nitride epitaxial semiconductor layer.

18 . The method of claim 14 , wherein:

providing the third III-nitride epitaxial semiconductor layer comprises ion implanting one or more of argon, nitrogen, helium, oxygen, or silicon into the third III-nitride epitaxial semiconductor layer to provide the non-conducting ion implanted zone.

19 . The method of claim 14 , wherein providing the second III-nitride epitaxial semiconductor layer comprises providing an outer region surrounding the terminal region, the outer region comprising a peripheral implanted zone having a peripheral zone conductivity.

20 . The method of claim 19 , wherein:

providing the third III-nitride epitaxial semiconductor layer comprises providing the tapered junction termination element comprising an implanted zone having a uniform implanted zone conductivity; and

the peripheral zone conductivity is equal to the uniform implanted zone conductivity.