APPARATUSES AND METHODS FOR SETTING A DUTY CYCLE ADJUSTER FOR IMPROVING CLOCK DUTY CYCLE
Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
1 . An apparatus comprising:
a duty cycle adjuster (DCA) configured to adjust a duty cycle of a clock signal; and
a mode register configured to store a first DCA code and a second DCA code in a plurality of opcodes, wherein the duty cycle is adjusted through the first DCA code and the second DCA code, wherein the first DCA code is for an upper byte and the second DCA code for a lower byte.
2 . The apparatus of claim 1 , wherein a first four of the plurality of opcodes store the first DCA code and a second four of the plurality of opcodes store the second DCA code.
3 . The apparatus of claim 1 , wherein the first DCA code and the second DCA code each comprise four bits.
4 . The apparatus of claim 3 , wherein four of the plurality of opcodes each store one bit of the first DCA code and another four of the plurality of opcodes each store one bit of the second DCA code.
5 . The apparatus of claim 1 , wherein the clock signal comprises an internal data clock signal.
6 . The apparatus of claim 1 , further comprising a clock divider, wherein the DCA is located before the clock divider.
7 . An apparatus comprising:
a memory controller configured to provide a data clock signal to a memory device and provide a duty cycle adjuster (DCA) code to the memory device, wherein the DCA code is one of a plurality of DCA codes, wherein a first set of the plurality of DCA codes cause the memory device to increase a duty cycle of a signal and a second set of the plurality of DCA codes cause the memory device to decrease the duty cycle of the signal.
8 . The apparatus of claim 7 , wherein the DCA code causes the memory device to adjust the duty cycle of the signal within a DCA range.
9 . The apparatus of claim 8 , wherein the DCA range is divided into a plurality of steps.
10 . The apparatus of claim 9 , wherein a difference between a first step and a second step is different than a difference between the second step and a third step.
11 . The apparatus of claim 9 , wherein the plurality of steps are nonlinear.
12 . The apparatus of claim 9 , wherein the plurality of steps comprises a step range between step 0 to step 7(−7).
13 . The apparatus of claim 7 , wherein at least one DCA code of the plurality of DCA codes causes the memory device to maintain the duty cycle of the signal.
14 . The apparatus of claim 7 , wherein the memory controller is configured to cause the DCA code to be written to a mode register of the memory device.
15 . The apparatus of claim 7 , wherein the memory controller is further configured to receive duty cycle monitoring results from the memory device, and the DCA code provided to the memory device is based, at least in part, on the duty cycle monitoring results.
16 . A method comprising:
providing from a controller to a memory, a data clock signal to cause the memory to generate an internal data clock signal; and
providing from the controller to the memory, a mode register write command and a duty cycle adjuster (DCA) code to cause the DCA code to be written to the mode register, and cause the memory to adjust a duty cycle of the internal data clock signal based on the DCA code.
17 . The method of claim 16 , further comprising:
providing from the controller to the memory, a mode register read command;
receiving at the controller from the memory, a duty cycle monitor result, wherein the DCA code provided is based, at least in part, on the duty cycle monitor result.
18 . The method of claim 16 , wherein adjusting the duty cycle comprises increasing the duty cycle, decreasing the duty cycle, or maintaining the duty cycle.
19 . The method of claim 16 , wherein the DCA code affects the duty cycle of the internal data clock signal for one or more of read, read32, write, write32, masked write, mode register read, read first-in-first-out (FIFO), write FIFO, read DQ calibration, and duty cycle monitor operations.
20 . The method of claim 16 , wherein the DCA code is one of a plurality of DCA codes and indicates a step size by which to adjust the duty cycle, wherein at least two of the DCA codes of the plurality of DCA codes have different step sizes.
21 . The method of claim 20 , wherein the step sizes are non-linear.
22 . The method of claim 16 , wherein the DCA code comprises a first DCA code for a first byte and a second DCA code for a second byte.