IP Library Patent Application 18903458
Patent Application
App. No. 18/903,458

SYSTEM AND METHOD FOR LOADING COEFFICIENT MATRICES IN A DIAGONALIZED PATTERN

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Quick Facts
Patent No.
US None
App. No.
18/903,458
Abstract

An example device includes a plurality of processing elements configured to perform a processing operation; memory cells interconnected with the processing elements, the memory cells organized into a plurality of wordlines, each wordline containing a set of columns; a controller interconnected with the processing elements, the controller configured to: for each coefficient vector of a coefficient matrix for the processing operation: assign a wordline identifier to each processing element; assign a column identifier to each processing element; write coefficients from the coefficient vector to the corresponding memory cell defined by the wordline identifier and the column identifier for each processing element; wherein the wordline identifiers and the column identifiers are assigned to the processing elements to load the coefficients of the coefficient vector in a diagonalized pattern in the memory cells.

Claims (31)

1 . A device comprising:

a plurality of processing elements configured to perform a processing operation;

memory cells interconnected with the processing elements, the memory cells organized into a plurality of wordlines, each wordline containing a set of columns;

a controller interconnected with the processing elements, the controller configured to:

for each coefficient vector of a coefficient matrix for the processing operation:

assign a wordline identifier to each processing element;

assign a column identifier to each processing element; and

write coefficients from the coefficient vector to the corresponding memory cell defined by the wordline identifier and the column identifier for each processing element; and

wherein the wordline identifiers and the column identifiers are assigned to the processing elements to load the coefficients of the coefficient vector in a diagonalized pattern in the memory cells.

2 . The device of claim 1 , wherein the plurality of processing elements are organized into pods, each pod including a predefined number of the processing elements.

3 . The device of claim 2 , wherein, to assign the wordline identifier to each processing element:

the controller is configured to send a set of wordline identifiers to each pod; and

each processing element in the pod is configured to select the wordline identifier from the set based on a wordline identifier pattern stored at the processing element.

4 . The device of claim 3 , wherein the processing element is further configured to apply a mask to a remainder of the wordline identifiers in the set.

5 . The device of claim 3 , wherein the processing element is configured to select the wordline identifier based on a sequence of the coefficient vector within a series of coefficient vectors defining the coefficient matrix.

6 . The device of claim 1 , wherein to assign the column identifier, each processing element is configured to select the column identifier based on a column identifier pattern stored at the processing element.

7 . The device of claim 6 , wherein the processing element is configured to select the column identifier based on a sequence of the coefficient vector within a series of coefficient vectors defining the coefficient matrix.

8 . A method comprising:

for each coefficient vector of a coefficient matrix for a processing operation:

assigning a wordline identifier to each processing element of a plurality of processing elements;

assigning a column identifier to each processing element; and

writing coefficients from the coefficient vector to a corresponding memory cell defined by the wordline identifier and the column identifier for each processing element; and

wherein the wordline identifiers and the column identifiers are assigned to the processing elements to load the coefficients in a diagonalized pattern in the memory cells.

9 . The method of claim 8 , wherein assigning the wordline identifier to each processing element comprises:

receiving, at each pod having a predefined number of processing elements, a respective set of wordline identifiers; and

selecting, by each processing element in the pod, the wordline identifier from the set based on a wordline identifier pattern stored at the processing element.

10 . The method of claim 9 , further comprising applying, by each processing element, a mask to a remainder of the wordline identifiers in the set.

11 . The method of claim 9 , comprising selecting, by each processing element, the wordline identifier based on a sequence of the coefficient vector in a series of coefficient vectors forming the coefficient matrix.

12 . The method of claim 8 , wherein assigning the column identifier comprises selecting, by each processing element, the column identifier based on a column identifier pattern stored at the processing element.

13 . The method of claim 12 , comprising selecting, by each processing element, the column identifier based on a sequence of the coefficient vector in a series of coefficient vectors forming the coefficient matrix.

14 . The method of claim 8 , further comprising, in response to loading all of the coefficient vectors of the coefficient matrix, proceeding with the processing operation.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2026
From: UNTETHER AI CORPORATION
To: AT-MEMORY COMPUTING LP
Reel/Frame 075495/0905 →
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2025
From: NATIONAL BANK OF CANADA
To: UNTETHER AI CORPORATION
Reel/Frame 071655/0897 →