Multi-Junction, Polarization-Controlled Vertical Cavity Surface Emitting Laser and Method of Fabrication Thereof

1 . A method of fabricating a vertical cavity surface emitting laser (VCSEL) comprising:

(a) forming or providing a first semiconductor wafer comprising, from a bottom to a top thereof, a first semiconductor substrate and a bottom distributed Bragg reflector (DBR);

(b) forming or providing a second semiconductor wafer comprising, from a bottom to a top thereof, a second semiconductor substrate and a semiconductor active region comprising at least one active subregion and a top cavity layer on a side of the at least one active subregion opposite the second semiconductor substrate, wherein each active subregion comprises:

a pair of cavity layers separated by a tunnel junction layer and a quantum well layer on a side of the pair of cavity layers opposite the second semiconductor substrate, or

a pair of cavity layers separated by a quantum well layer and a tunnel junction layer on a side of the pair of cavity layers opposite the second semiconductor substrate;

(c) coupling the bottom DBR and the semiconductor active region with the second semiconductor substrate disposed on a side of the semiconductor active region opposite the bottom DBR and then removing the second semiconductor substrate;

(d) following the removal of the second semiconductor substrate, forming on a side of the semiconductor active region opposite the bottom DBR a top DBR; and

(e) forming on all or part of the at least one active subregion of the semiconductor active region a current confinement structure.

2 . The method of claim 1 , wherein:

step (b) includes the semiconductor active region including two active subregions; or

step (c) includes coupling the bottom DBR and the semiconductor active region with a dielectric layer therebetween.

3 . The method of claim 2 , further comprising, prior to step (c), forming the dielectric layer on a side of the bottom DBR opposite the first semiconductor substrate, on a side of the semiconductor active region opposite the second semiconductor substrate, or on both, whereupon step (c) includes coupling the bottom DBR and the semiconductor active region with the dielectric layer therebetween.

4 . The method of claim 2 , wherein the dielectric layer has a refractive index n≤1.5.

5 . The method of claim 1 , wherein:

the top DBR comprises a first plurality of semiconductor layers; and

the bottom DBR comprises a second plurality of semiconductor layers.

6 . The method of claim 5 , wherein the first plurality of semiconductor layers of the top DBR and the second plurality of semiconductor layers of the bottom DBR are different.

7 . The method of claim 1 , further comprising forming a grating structure:

on a side of the top DBR opposite the at least one semiconductor active region; or

between layers of the top DBR; or

between the semiconductor active region and the top DBR; or

between the bottom DBR and the semiconductor active region.

8 . The method of claim 1 , wherein the current confinement structure of step (e) is formed prior to or after step (c).

9 . The method of claim 2 , wherein the dielectric layer has a thickness of λx/4, where x is an odd number and λ is a wavelength of an optical signal produced by the VCSEL.

10 . The method of claim 2 , wherein the dielectric layer includes one or more voids, spaces, or pockets.

11 . A vertical cavity surface emitting laser (VCSEL) comprising from a bottom to a top thereof:

a semiconductor substrate;

a bottom distributed Bragg reflector (DBR);

a semiconductor active region comprising at least one active subregion; and

a top DBR.

12 . The VCSEL of claim 11 , wherein the VCSEL further comprises one of the following:

a dielectric layer between the bottom DBR and the semiconductor active region; or

the semiconductor active region includes two active subregions.

13 . The VCSEL of claim 12 , wherein the dielectric layer has a refractive index n≤1.5.

14 . The VCSEL of claim 11 , further comprising a current confinement structure disposed on at least part of the semiconductor active region.

15 . The VCSEL of claim 14 , wherein the current confinement structure is formed by oxidation, ion implantation, or by etching and overgrowth of the at least part of the semiconductor active region.

16 . The VCSEL of claim 12 , further including a grating structure:

on a side of the top DBR layer opposite the semiconductor active region; or

between layers of the top DBR; or

between the semiconductor active region and the top DBR; or

between the bottom DBR and the semiconductor active region.

17 . The VCSEL of claim 11 , wherein the semiconductor active region comprises one or more active subregions each comprising one of the following:

(a) a quantum well layer and a pair of cavity layers separated by a tunnel junction layer on a side of the quantum well layer opposite the dielectric layer; or

(b) a tunnel junction layer and a pair of cavity layers separated by a quantum well layer on a side of the tunnel junction layer opposite the dielectric layer.

18 . The VCSEL of claim 12 , further comprising a top cavity layer between the at least one active subregion and the dielectric layer.

19 . The VCSEL of claim 17 , further comprising a current confinement structure disposed on at least part of each active subregion.

20 . The VCSEL of claim 19 , wherein the current confinement structure is disposed on each cavity layer and each tunnel junction layer of each active subregion.

21 . The VCSEL of claim 20 , wherein the current confinement structure is disposed on the quantum well layer of at least one active subregion.

22 . The VCSEL of claim 12 , wherein the dielectric layer has a thickness of λx/4, where x is an odd number and λ is a wavelength of an optical signal produced by the VCSEL.